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RX - 4803 SA / LC
5) FSEL0,1 ( FOUT frequency Select 0, 1 ) bits
The combination of these two bits is used to set the FOUT frequency.
FSEL0,1
Write/Read
6) TSEL0,1 ( Timer Select 0, 1 ) bits
The combination of these two bits is used to set the countdown period (source clock) for the fixed-cycle timer
interrupt function (four settings can be made).
TSEL0,1
Write/Read
8.2.6. Flag register
Address
Flag register
E
∗1)
The default value is the value that is read (or is set internally) after powering up from 0 V.
∗2)
"o" indicates write-protected bits. A zero is always read from these bits.
∗3)
"−" indicates a default value is undefined.
• This register is used to detect the occurrence of various interrupt events and reliability problems in internal data.
1) UF ( Update Flag ) bit
If set to "0" beforehand, this flag bit's value changes from "0" to 1" when a time update interrupt event has
occurred. Once this flag bit's value is "1", its value is retained until a "0" is written to it.
∗
For details, see "8.4. Time Update Interrupt Function".
2) TF ( Timer Flag ) bit
If set to "0" beforehand, this flag bit's value changes from "0" to 1" when a fixed-cycle timer interrupt event has
occurred. Once this flag bit's value is "1", its value is retained until a "0" is written to it.
∗
For details, see "8.3. Fixed-cycle Timer Interrupt Function".
3) AF ( Alarm Flag ) bit
If set to "0" beforehand, this flag bit's value changes from "0" to 1" when an alarm interrupt event has occurred.
Once this flag bit's value is "1", its value is retained until a "0" is written to it.
∗
For details, see "8.5. Alarm Interrupt Function".
4) EVF ( Event Flag ) bit
If set to "0" beforehand, this flag bit's value changes from "0" to 1" when a event input interrupt has occurred.
Once this flag bit's value is "1", its value is retained until a "0" is written to it.
5) VLF ( Voltage Low Flag ) bit
This flag bit indicates the retained status of clock operations or internal data. Its value changes from "0" to "1"
when data loss occurs, such as due to a supply voltage drop. Once this flag bit's value is "1", its value is
retained until a "0" is written to it.
When after powering up from 0 V this bit's value is "1" .
FSEL1
FSEL0
(bit 3)
(bit 2)
0
0
0
1
1
0
1
1
TSEL1
TSEL0
(bit 1)
(bit 0)
0
0
0
1
1
0
1
1
Function
bit 7
(Default)
(0)
FOUT frequency
32768 Hz Output
1024 Hz Output
1 Hz Output
32768 Hz Output
Source clock
/ Once per 244.14 µs
4096 Hz
64 Hz
/ Once per 15.625 ms
"Second" update / Once per second
"Minute" update / Once per minute
bit 6
bit 5
bit 4
UF
TF
(0)
(−)
(−)
Page - 11
∗ Default
bit 3
bit 2
bit 1
AF
EVF
VLF
(0)
(1)
(−)
ETM33E-04
bit 0
VDET
(1)
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