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RX - 4803 SA / LC
7.2. AC Characteristics
Item
CLK clock cycle
CLK H pulse width
CLK L pulse width
CLK rise and fall time
CLK setup time
CE setup time
CE hold time
CE recovery time
CE enable time
Write data setup time
Write data hold time
Read data delay time
DO output switching time
DO output disable time
DI/DO conflict avoiding time
FOUT duty
Timing chart
t
CS
C E
t
CLKS
CLK
• Read
D I
D O
• Write
D I
D O
∗ If DI and DO pins are wired-OR connected to make it to 3 lines form, secure tzz to avoid bus conflict.
Symbol
Condition
t
CLK
t
W H
t
W L
t
RF
t
CLKS
t
CS
t
CH
t
CR
t
W CE
t
DS
t
DH
t
C
=50 pF
L
RD
t
ZR
C
=50 pF
L
t
RZ
R
=10 kΩ
L
t
ZZ
t
/ t
50% V
level
W
DD
t
RF
t
RF
80%
20%
t
t
DS
DH
M 3
M 2
Hi-Z
M 3
M 2
Hi-Z
Page - 5
* Unless otherwise specified, GND = 0 V , Ta = −40 °C to +85 °C
2.4V ≤ V
< 4.5V
DD
Min.
Max.
500
220
220
60
50
200
200
300
0.95
100
100
200
50
200
0
40
60
t
WCE
t
CLK
t
t
WL
WH
A 0
t
RD
t
ZZ
D 7
D 6
t
ZR
A 0
D 7
D 6
4.5V ≤ V
≤ 5.5V
DD
Unit
Min.
Max.
350
155
155
40
25
150
150
200
0.95
50
50
150
20
150
0
40
60
t
t
CH
CR
t
RZ
D 0
D 0
ETM33E-04
ns
ns
ns
ns
ns
ns
ns
ns
s
ns
ns
ns
ns
ns
ns
%
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