Control Register / Flag Register - Epson RTC-9701JE Applications Manual

RTC - 9701 JE

11.5. Control register / Flag register

Address Function
D Extension reg.
E Flag reg.
F Control reg.
11.5.1. Control register
l TEST
This bit is used by EPSON for testing. Be sure to set it to "0".
l WADA
This bit sets either the WEEK alarm or the DAY alarm. For details, see the Time alarm section [11.3.1.].
l UDUTY, USEL, UIE
This is the time update interrupt bit. For details, see the Time update interrupt section [11.4.2.].
l TSEL
This is the source clock setting bit for the timer. For details, see the Variable interval timer section [11.4.1.].
l EXIE
This is the enable bit for the VEX voltage decrease detection circuitry. For details, see the VEX voltage decrease alarm
section [11.3.2.1.].
l VLIE
This is the enable bit for the V
section [11.3.2.2.].
l TIE
This is the enable bit for the timer. For details, see the Variable interval timer section [11.4.1.].
l AIE
This is the enable bit for the time alarm. For details, see the Time alarm section [11.3.1.].
11.5.2. Flag register
This register is the flag register. For each event (alarm and interval timer) generated, "1" is set. Set it to "0" to clear. To
keep the corresponding register state, set it to "1" (mask).
l VLF2
This bit is the flag that records oscillation circuitry voltage decrease. For details, see the Oscillation circuitry voltage
decrease flag (VLF2) section [11.3.2.3.].
l UF
This bit becomes "1" when time update occurs. For details, see the Time update interrupt section [11.4.2.].
l TF
During the interval timer, this bit is set to "1" at the Negative Edge of the /TIRQ. For details, see the Variable interval timer
section [11.4.1.].
l EXF
This bit becomes "1" when VEX voltage decrease occurs. For details, see the VEX voltage decrease alarm section
[11.3.2.1.].
l VLF
This bit becomes "1" when VDD2 voltage decrease occurs. For details, see the V
[11.3.2.2.].
l AF
This bit becomes "1" when time match alarm occurs. For details, see the Time alarm section [11.3.1.].
bit 7 bit 6 bit 5
TEST WADA UDUTY USEL
VLF2 ¡ UF
¡ ¡ UIE
voltage decrease detection circuitry. For details, see the V
DD2
Page-13
bit 4 bit 3 bit 2 bit 1
¡ ¡
TSEL1 TSEL0
TF AF EXF VLF
TIE AIE EXIE VLIE
bit 0 R/W Comments
R/W
¡ R/W
¡ R/W
voltage decrease alarm
DD2
voltage decrease alarm section
DD2
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