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RTC - 8564 JE/NB
8. How to use
8.1. Register table
Address
Function
00
Control 1
01
Control 2
02
Seconds
03
Minutes
04
05
06
Weekdays
07
Months / Century
08
09
Minute Alarm
0A
Hour Alarm
0B
Day Alarm
0C
Weekday Alarm
0D
CLKOUT frequency
0E
Timer control
0F
Notes ;
(1)
When the power is turned on initially, the FD1 and FD0 bits are cleared to 0. Also, FE and VL bits are set to 1, but
because other the register values of other bits are unknown, always make their initial settings. When doing so,
do not make settings for date and time that are impossible. We do not guarantee proper operation of the clock
for such settings.
(2)
While there is a bit at address 00 for setting the test mode, the test mode is a special operation mode that is used
by EPSON for testing devices. Be sure not to set it to 1. If it is set to the test mode, all operations of the device will
not be guaranteed. Therefore, be careful when access to address 00.
(3)
Be sure to set bit '0' of address 00,01 (Control1,2) to zero.
(4)
All count data at address 02 through 05 and 08 through 0B is in the BCD format.
Write to bit ' × ' is not possible, and its read-out value is not fixed. Be sure to mask it after bit ' × ' is read out.
(5)
8.2. Register description
8.2.1. Control register 1
Address
Function
00
Control 1
• TEST
The two TEST bits are for testing devices. Therefore be sure to set them to zeros. If they are accidentally set
to 1, they may immediately modify the clock data or result in abnormal time.
• STOP
When this bit becomes zero, the device's time function operates. When it is set to 1, all internal count down
chain are goes into the zero clear state. If it is cleared together with the time reporting, the time can be
adjusted accurately up to one second. As for output of CLKOUT,
STOP doesn't affect frequency output of 32768 Hz.But output stops at the time of frequency setting except
32768 Hz by STOP =1.
bit 7
TEST
0
VL
×
×
Hours
×
Days
×
C
Years
80
AE
AE
AE
AE
FE
TE
Timer
128
bit 7
bit 6
TEST
0
bit 6
bit 5
bit 4
0
STOP
0
×
0
TI / TP
40
20
10
40
20
10
×
20
10
×
20
10
×
×
×
×
×
10
40
20
10
40
20
10
×
20
10
×
20
10
×
×
×
×
×
×
×
×
×
64
32
16
bit 5
bit 4
bit 3
STOP
0
TEST
Page - 5
bit 3
bit 2
bit 1
TEST
0
0
AF
TF
AIE
8
4
2
8
4
2
8
4
2
8
4
2
×
4
2
8
4
2
8
4
2
8
4
2
8
4
2
8
4
2
×
4
2
×
×
FD1
×
×
TD1
8
4
2
bit 2
bit 1
bit 0
0
0
0
MQ - 322 - 04
bit 0
0
TIE
1
1
1
1
1
1
1
1
1
1
1
FD0
TD0
1
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