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RX - 4803 SA / LC
8.11. Note
about read-out method of a 1/100s register
RA-4803 is equipped with a 1/100s register.
As for 1/100 counters, it is worked in very fast clock than second.
Therefore, as for the count operation of each, behavior in a chip access hold facility (P.8 reference) operation is different.
When using a 1/100s register, be careful as follows.
Behavior, when access hold function worked.
When communication to a clock counter of an RTC started, by access hold facility, update in the time can stop hold
automatically.
However, as for 1/100 second counters, data cannot stop hold, and count is continued.
As for 1/100 value, it is examined data by IC circuit, and it is captured to 1/100s register.
Therefore, there is case lost continuity of data in 1/100 second data and time data when 1/100 second digits are captured
just after a second updates.
This phenomenon occurs in restrictive timing, but internal Time and date are correct and internal updates are correct.
A lag of a readout result is -1 second at the maximum.
Read-out method of 1/100 second digits to prevent mismatching of the time
Method 1
Method to read two times of 1/100 second digits
Step1:
please read 1/100 second digits and time data, and stored those.
Step2:
Please read only 1/100 second digits again.
Please complete Step2 within 10ms from Step1.
Step3:
If two 1/100 second digits are same values, please advance next.
When two values are different, please return to Step1.
Note
Between Step2 and Step1, please put CE=LOW by all means.
Method 2
Method to use an interruption flag of the fixed period interrupt function.
Step1
Please clear USEL bit of address Dh in a zero.
It is update interruption of sec.
Please clear UF bit of address Eh in a zero.
Step3:
Please read time data and 1/100 data.
Please read UF bit.
Step5:
Please adopt the data that I read in case of UF=0.
Please cancel the data that I read in case of UF=1.
Step6:
When it is executed again, return to Step2.
When second is updated, a UF bit is set to 1.
Therefore it must be executed Step2 and 4 within one second.
Please complete Step4 within 1sec from Step2.
(recommendation,:, lower than 10ms)
Please divide Step3 and Step4 by CE=LOW.
Page - 27
ETM33E-04
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