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12.2. Register table
Address h
10
11
12
13
14
15
16
17
Setting data
18
19
1A
Timer Counter 0
1B
Timer Counter 1
1C
Extension Register
1D
1E
Control Register
1F
Setting data
Address h
20
|
2F
Address h
30
31
32
Note
During the initial power-on (from 0 V) and if the value of the VLF bit is "1" when the VLF bit is read, be sure to
initialize all registers before using them.
When doing this, be careful to avoid setting incorrect data as the date or time, as timed operations cannot be
guaranteed if incorrect date or time data has been set.
1.
During the initial power-on (from 0 V), the power-on reset function sets "1" to the VLF bit.
Since the value of other registers is undefined at this time, be sure to reset all registers before using them.
2.
The TEST, bit are Epson test bits.
Be sure to write "0" by initializing before using the clock module. Afterward, be sure to set "0" when writing.
The four TEST* bits are undefined when read. Those bits should be masked after being read.
3.
The '
' mark indicates a write-prohibited bit, which returns a "0" when read.
4.
The ' • ' mark indicates a read/write-accessible RAM bit for any data.
RX8010SJ
ETM37E-07
Function
bit 7
SEC
MIN
HOUR
WEEK
DAY
MONTH
YEAR
80
Reserved
1
MIN Alarm
AE
HOUR Alarm
AE
WEEK Alarm
AE
DAY Alarm
128
32768
FSEL1
Flag Register
TEST
0
Function
bit 7
RAM
Function
bit 7
Digital offset
DTE
Reserved
Setting data
0
IRQ Control
Setting data
0
Seiko Epson Corporation
12.Overview of Functions and Description of
bit 6
bit 5
bit 4
40
20
40
20
20
6
5
20
40
20
-
-
-
1
0
40
20
•
20
6
5
•
20
64
32
16384
8192
4096
FSEL0
USEL
UF
STOP
UIE
STOP
UIE
bit 6
bit 5
bit 4
User Register
128 bit ( 16 word x 8 bit )
bit 6
bit 5
bit 4
L7
L6
0
0
-
-
0
0
bit 3
bit 2
10
8
4
10
8
4
10
8
4
4
3
2
10
8
4
10
8
4
10
8
4
-
-
-
1
1
0
10
8
4
10
8
4
4
3
2
10
8
4
16
8
4
2048
1024
TE
WADA TSEL2 TSEL1 TSEL0
TF
AF
TIE
AIE
TSTP
TIE
AIE
TSTP
bit 3
bit 2
bit 3
bit 2
L5
L4
L3
-
-
-
0
1
0
-
TMPIN
FOPIN1 FOPIN0
0
0
TMPIN
FOPIN1 FOPIN0
Registers
bit 1
bit 0
2
1
2
1
2
1
1
0
2
1
2
1
2
1
-
-
0
0
2
1
2
1
1
0
2
1
2
1
512
256
VLF
-
-
0
0
bit 1
bit 0
bit 1
bit 0
L2
L1
-
-
0
0
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INDEX
16
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