OLIMEX LPC-P1227 User Manual page 11

OLIMEX© 2012
Analog peripherals
•
Power
•
Unique device serial number for identification.
•
3.3 V power supply
•
1
For comprehensive information on the microcontroller visit the NXP web page for a datasheet.
At the moment of writing the microcontroller datasheet can be found at the following link:
http://ics.nxp.com/products/lpc1000/datasheet/lpc122x.pdf
Downloaded from Elcodis.com electronic components distributor
✗ CRC engine.
✗ Two UARTs with fractional baud rate generation and internal FIFO. One UART
with RS-485 and modem support and one standard UART with IrDA.
✗ SSP/SPI controller with FIFO and multi-protocol capabilities.
✗ I2C-bus interface supporting full I2 C-bus specification and Fast-mode Plus with a
data rate of 1 Mbit/s with multiple address recognition and monitor mode. I2C-bus
pins have programmable glitch filter.
✗ 55 General Purpose I/O (GPIO) pins with programmable pull-up resistor, open-drain
mode, programmable digital input glitch filter, and programmable input inverter.
✗ Programmable output drive on all GPIO pins. Four pins support high-current output
drivers.
✗ All GPIO pins can be used as edge and level sensitive interrupt sources.
✗ Four general purpose counter/timers with four capture inputs and four match outputs
(32-bit timers) or two capture inputs and two match outputs (16-bit timers).
✗ Windowed WatchDog Timer (WWDT); IEC-60335 Class B certified.
✗ One 8-channel, 10-bit ADC.
✗ Two highly flexible analog comparators. Comparator outputs can be programmed to
trigger a timer match signal or can be used to emulate 555 timer behavior.
✗ Three reduced power modes: Sleep, Deep-sleep, and Deep power-down.
✗ Processor wake-up from Deep-sleep mode via start logic using 12 port pins.
✗ Processor wake-up from Deep-power down and Deep-sleep modes via the RTC.
✗ Brownout detect with three separate thresholds each for interrupt and forced reset.
✗ Power-On Reset (POR).
✗ Integrated PMU (Power Management Unit).
Page 11 of 25
LPC-P1227 User's Manual