Centronics Controller - Fujitsu ULTIMA90 Maintenance Manual

5.3.2.3 Centronics Controller

Figure 5.3.8 is an interface control block diagram.
[Centronics interface control]
The Centronics interface controller uses the Centronics controller built in the FPGA as shown in Figure 5.3.8
The INPRM and EXPRM signals, which are forcible reset signals from the host, are used as interrupt signals after noise is
removed from them by sampling in the anti-noise interrupt control circuit.
This printer supports nibble mode conforming to IEEE Std 1284-1994.
The following shows the circuits used for two-way Centronics control.
[Centronics control circuit]
Figure 5.3.9 shows a general timing chart for the Centronics control circuit.
The Centronics control circuit latches received data DATA1 to DATA8 to the internal register at the falling edge of data
strobe signal *DSTB, and simultaneously sends an interrupt signal to the external interrupt control circuit to inform the
MPU of the receipt of data.
The MPU checks that external data has been input, reads the data, and then stores it in SRAM.
After the interrupt is released from the MPU, BUSY is reset and *ACK is sent
DATA1-8
Buffe
r
Centronics
Driver
Centronics
/
receive
r
Figure 5.3.8 Interface control block diagram
FPGA
DSTB,DATA1:
Centronics
AFXT,SLCTI
control
ACK,BUSY,P
SLCT,FAUL
RINF1 3
INPRM,EXPRM
.
150
MPU
interrup