Infineon BGT24LTR11 User Manual page 19

User's guide to BGT24LTR11
XENSIV™ 24 GHz radar MMIC
Table of contents
Divided Signal CCU
Figure 21 Decision function
The length of the counting gate has a strong impact on the accuracy of the VCO frequency measurement.
At the start and at the end of the counting gate (N times the period of the divider output signal), there is a
systematic error caused by the period of the MCU master clock. Longer counting gate time (i.e., a greater
number of periods of the MCU master clock – e.g., 80 MHz – are counted) results in a lower impact of this
systematic error on VCO frequency measurement accuracy. However, longer counting gate time results in a
longer ON time for the BGT24LTR11 and impacts the overall power consumption.
Divider output
T_masterclk
(f_q1)
Master clock
01 01
(f_masterclk)
01
1st rising
edge (01)
Desired VCO freq (f_desired): 24.025 GHz
Divider output frequency (f_q1): 24.025 GHz/8192: 2.9327 MHz
Master clock frequency (f_masterclk): 80 MHz
Divider output period (t_q1)= 1/2.9327 MHz = 340.98 ns
Master clock period (t_masterclk): 1/80 MHz: 12.5 ns
Number of divider output periods (N) = 100
Counting gate time (T_gate) = N*t_q1 = 100*340.98 ns = 34098 ns
No. of ticks (N_ticks) = T_gate/t_masterclk = 34098ns/12.5 ns = 2728
Obtained VCO freq (f_measured): (8192*N/N_ticks*t_masterclk) = 8192*100/2728*12.5ns = 24.023 GHz
Error = f_desired – f_measured = 24.025 – 24.023 GHz = 2 MHz
Figure 22 Systematic timing error at the start and the end of the counting gate
Application note
T_gate =N*t_q1= counting gate time
t_q1
02 02 03 03 04 04
05 05
02 03 04 05
smaller
</> wanted
frequency
higher
06 06 07 07 08 08 09 09
06 07 08 09
19
increase bits
new bit value
lower bits
t_q1
10 10 11 11 12 12 13 13
10 11 12 13
Counting error
VCO freq is lower
Counting error
VCO freq is higher
14 14 15
14 15
Last rising=15
Counter = 15
N_ticks
Revision 1.50
2023-02-14