Infineon BGT24LTR11 User Manual page 18

User's guide to BGT24LTR11
XENSIV™ 24 GHz radar MMIC
Table of contents
Figure 20 shows a block diagram on how to set up the system.
Connect the VCC_DIV and VCC_PTAT to VCC to set the divider ratio to 8192.
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Connect the divider output to a Capture & Compare Unit (CCU) of the MCU to determine the frequency of the
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oscillator.
Connect the MCU's digital-to-analog converter (DAC) output to the V_TUNE of BGT24LTR11 through a 2-
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stage RC filter to provide a tuning voltage to the VCO.
The 2-stage RC DAC filter is required to filter the noise and reject the higher unwanted frequencies. It should
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be placed as close to the VCO V_TUNE input as possible.
The design of this RC DAC filter is critical to avoid VCO modulation with noise and spurs. For a stepped-
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FMCW approach, the DAC filter needs to be optimized for the update rate based on the chirp time (Tc) and
number of samples per chirp (Nsamples). For example, for a Tc = 1500 ms and Nsamples = 256, the update
rate is 1500 ms / 256 = 6 µs (step-time). Therefore, the RC time constant for the DAC filter should be designed
to settle at 5 µs (90...95% of the desired voltage step). This lets the DAC's output voltage and consequently
the VCO frequency to be in a steady state at the end of step-time when the baseband analog-to-digital
converter (ADC) is triggered for measurement.
As an option, connect the V_PTAT output from BGT24LTR11 to an ADC channel of the MCU to determine the
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temperature of the chip. This would allow compensating the frequency shift due to temperature changes
and would reduce the need to re-calibrate the SW PLL very frequently.
4.3.2 Concept
As shown in Figure 20, the DAC of the MCU is used to generate a tuning voltage for the VCO input. Vtune is
generated by the DAC for the start frequency and then filtered in the RC-filter (2 stages). According to the Vtune
input, the VCO produces the TX/LO signal. The VCO signal is also fed into a frequency divider and gets divided
by a factor of 8192. This divided signal is captured by the CCU in the MCU. The divider output signal is measured
by counting the number of rising/falling (or both) edges of the MCU's master clock inside a certain number of
divider output signal periods (counting gate). The measured frequency is then compared with the required
start frequency (24.025 GHz / 8192 = 2.9327 MHz). The difference between the measured and required
frequency is then evaluated in the decision function. Depending on the result, the bit value gets adapted, and
the loop starts again until the measured and wanted frequency to agree within a certain margin. This routine is
repeated for the stop frequency as well (24.225 GHz / 8192 = 2.9571 MHz).
Note: To prevent out of band emissions, a guard band of 25 MHz between ISM band edges and the the
Start/Stop frequency of the stepped-FMCW sweep is implemented. Therefore, the chirps have a
bandwidth of 200 MHz (24.025 GHz - 24.225 GHz) and calibration is done every frame. The guard
band would change depending on the circuitry implemented and how often the calibration is
done.
Note: The 200 MHz bandwidth is split up into a certain number of points per chirp (Nsamples). Nsamples
is related to unambiguous range and therefore impacts the maximum range (Rmax
=Nsamples*∆R), where Rmax is the maximum achievable range and ∆R is the range resolution.
Application note 18 Revision 1.50
2023-02-14