Infineon BGT24LTR11 User Manual page 16

User's guide to BGT24LTR11
XENSIV™ 24 GHz radar MMIC
Table of contents
4.2 VCO control using a PLL
A PLL can be connected to the BGT24LTR11 to control the VCO as shown in Figure 19.
To implement this, the frequency divider needs to be set to a ratio of 16 by connecting VCC_PTAT to GND.
The VCO output is split into the TX antenna path and the local oscillator (LO) path. Furthermore, the VCO
output signal gets divided by a factor of 16 (prescaler), producing a 1.5 GHz divider output signal for the PLL.
In the PLL, further dividers (N-divider) are applied to the input divider signal to further reduce the frequency.
The phase detector (PD) in PLL compares the N-divider output signal with the reference from a crystal oscillator
to control the PLL charge pump (CP). The CP
loop filter (LF). VTUNE finally controls the VCO frequency to achieve a full signal fit between N-divider output
signal and the reference signal to achieve a frequency and phase lock.
TX
TX_ON
Figure 19 Block diagram of VCO control using a PLL
Application note
is converted into an analog VCO tuning signal (VTUNE) via the
out
VCC
VCC
MPA
f-Div
(/16)
C1
DIV
VCC_DIV
Loop filter
f
div
f
ref
PLL
Crystal
Osc.
IFI IFQ
BGT24LTR11
IFQ
90°
0°
IFI
R_TUNE
PTAT
V_PTAT
VTUNE
CP
out
16
RFIN
LNA
VCC_PTAT
Revision 1.50
2023-02-14