Operation - Infineon BGT24LTR11 User Manual

User's guide to BGT24LTR11
XENSIV™ 24 GHz radar MMIC
Table of contents
For a divider output frequency of ~3 MHz and an MCU master clock of 80 MHz, we recommend counting over
100 periods (N=100) of the divider output signal, to get a maximal frequency measurement error < 10 MHz.
Another way to reduce this systematic timing error would be to increase the master clock frequency (for
example, a master clock of 120 MHz instead of 80 MHz will reduce the error as the T_clock time will be reduced
from 12.5 ns to 8.3 ns, and the maximal frequency measurement error is < 6 MHz). However, higher master clock
frequency leads to higher power consumption by the microcontroller.
Note: To stay inside the ISM band during the frequency search process, the smart search for the start
frequency always begins with a DAC value generating a VCO frequency above the desired start
frequency. Similarly, stop frequency search should begin below the desired stop frequency.
With the achieved start- and stop frequency DAC values (and Vtune values) a linear interpolation can be done
and an LUT "DAC value vs. VCO Frequency" is generated. The contents of the LUT are clocked (e.g., via DMA) to
the DAC and hence provide the modulation of the VCO.
To further improve the linearity of the chirps, it is possible to do a search for three or more frequency points
and perform a polynomial approximation between these points to fit the Vtune vs. VCO Frequency in a more
precise non-linear LUT. Also, by utilizing the chip's temperature information (e.g., via PTAT), the LUT can be re-
calibrated only when there is a change in the chip's temperature. This would reduce the need to calibrate the
LUT very frequently.
4.3.3

Operation

To get the best frequency measurement accuracy (No VCO pulling effect), TX should remain ON during the
1.
frequency search process. VTUNE must keep the VCO in the ISM band all the time by following the 'smart
search' methodology from section 4.3.2.
Check the temperature of the chip using the V
2.
Set the DAC to a fixed starting value for start frequency search to generate a VTUNE voltage for the VCO.
3.
CCU measures the frequency of the divider output signal. The desired start frequency is already known and
4.
compared with the measured frequency. The DAC value is then adjusted using a decision function to
achieve the best possible match for the desired frequency. (iterative frequency search process)
Once the DAC value for the start frequency is found, repeat the steps 3&4 to search the appropriate DAC
5.
value for the stop frequency.
Using these start and stop DAC values, generate an LUT that gives the DAC values corresponding to different
6.
VCO frequencies.
Use the generated LUT for the modulation of the VCO by clocking the LUT values (e.g., via DMA) to the DAC.
7.
Feed the DAC output to the DAC filter. After the DAC filter output has settled on the step, take the ADC
measurement, and then move the DAC to the next LUT step, creating a stepped-FMCW chirp.
Check the temperature of the chip. If the temperature changed, or it is the beginning of a new frame go to 1
8.
else go to 7 to generate the next chirp.
Application note
. (if implemented)
PTAT
20 Revision 1.50
2023-02-14