Toshiba PORTEGE R300 Maintenance Manual page 69

Table 2-4 Debug port (Boot mode) error status (3/10)
D port status
F100H IRT_START
Process of cache control for
HyperThreading
Prohibition of cache
Initialization of H/W (before DRAM
recognition)
Initialization of PIT channel 1
F101H IRT_INI_SPREG_END
Check of DRAM type and size
(at cold boot)
SM-RAM stack area test
F102H
Cache configuration
Cache permission (L1/L2 Cache)
CMOS access test (at cold boot)
Battery level check of CMOS
CMOS checksum check
Initialization of CMOS data (1)
Setting of IRT status
Storing DRAM size in CMOS
Cache configuration
F103H
IRT_RSM_BRANCH
Resume branch (at cold boot)
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Inspection items
2 Troubleshooting Procedures
Details
Initialization of MCHM
nitialization of ICH4M.D31.Func0
I
Initialization of ICH4M.D31.Func1
Initialization of USB.Func0,1,2,7
Initialization of ICH4M.D31.Func3
Initialization of ICH4M.D31.Func5
Initialization of FLUTE
(Setting the refresh interval to "30μs")
When unsupported memory is connected,
becoming HLT after beep sound (HLT when
DRAM size is 0)
HLT When it can not be used as a stack
(HLT when an error is detected)
(Setting of boot status and IRT busy flag, The rest
bits are 0)
Not resume when a CMOS error occurred
Not resume when resume status code is not set
Resume error check
S3 returning error (ICH)
Resume error F170 RSM_UNKNOWN_ERR
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