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NXP Semiconductors K32W061 User Manual

NXP Semiconductors K32W061 User Manual

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K32W061

K32W061/K32W041 User

Manual

UM11323

Rev. 1.1 — June 2020

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Arm Cortex-M4, microcontroller, Zigbee, Thread, Bluetooth Low Energy

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K32W061/41 User Manual

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Page 1 K32W061 K32W061/K32W041 User Manual UM11323 Rev. 1.1 — June 2020 User manual Document information Info Content Keywords Arm Cortex-M4, microcontroller, Zigbee, Thread, Bluetooth Low Energy Abstract K32W061/41 User Manual...
Page 2 UM11323 NXP Semiconductors K32W061/41 User manual 11111111 Revision history Date Description • 2020/06 Updated ISP usage restrictions in the Section 38.8 “Usage restrictions”. • Updated to reserve the CT32B_IR[7:6]. 2020/04 Initial public release Contact information For more information, please visit: http://www.nxp.com...
Page 3 Ultra-low current consumption in radio receive and radio transmit modes allows use of coin cell batteries. K32W061/041 has 640 KB embedded Flash, 152 KB RAM and 128 KB ROM memory. The embedded flash can support Over The Air (OTA) code download to applications. The...
Page 4 Standby power controller • Up to 22 Digital IOs (DIO) • 1 x Quad SPIFI for reading or writing to external flash device • NTAG NFC Forum Type 2 on K32W061 only • Random Number Generator engine • AES engine •...
Page 5 UM11323 NXP Semiconductors Chapter 1: Introductory Information 1.2.2 Radio features • 2.4 GHz IEEE 802.15.4 compliant • 2.4 GHz Bluetooth Low Energy 5.0 compliant • Receive current 4.3 mA • IEEE 802.15.4 receiver sensitivity -100 dBm • Bluetooth Low Energy 5.0 2 Mbps high data rate •...
Page 6 UM11323 NXP Semiconductors Chapter 1: Introductory Information 1.3 Block diagram Debug Quad GPIO DMIC Controller USART 1 SPI 1 Access Cortex-M4 SPIFI (22I/Os) Controller Port (19channels) with MPU AHB Multi-Layer Matrix APB Bridge 1 FLASH SRAM 0 SRAM 1 Hash...
Page 7 UM11323 NXP Semiconductors Chapter 1: Introductory Information APB peripherals are connected to the AHB matrix via two APB buses using separate slave ports from the multilayer AHB matrix. This allows for better performance by reducing collisions between the CPU and the DMA controller, and also for peripherals on the asynchronous bridge to have a fixed clock that does not track the system clock.
Page 8 UM11323 NXP Semiconductors Chapter 1: Introductory Information A 3-stage pipeline is employed so that all parts of the processing and memory systems can operate continuously. Typically, while one instruction is being executed, its successor is being decoded, and a third instruction is being fetched from memory.
Page 9 Chapter 2: Memory Map Rev. 1.1 — June 2020 User manual 2.1 General description The K32W061/41 incorporates several distinct memory regions. Figure 1 shows the overall map of the entire address space from the user program viewpoint following reset. The APB peripheral area (detailed in...
Page 10 UM11323 NXP Semiconductors Chapter 2: Memory Map 32-bit Words 0xFFFF_FFFF Reserved (Do not access) 0xE00F_FFFF Private Peripheral Bus (External) 0xE004_0000 0xE003_FFFF Private Peripheral 768 KBytes Bus (Internal) 0xE000_0000 Reserved (Do not access) 0x400B_1FFF IEEE 802.15.4 MAC 4 Kbytes 0x400B_1000 0x400B_0FFF IEEE 802.15.4 MODEM...
Page 11 Chapter 2: Memory Map 2.1.3 AHB multilayer matrix The K32W061/41 uses a multi-layer AHB matrix to connect the CPU buses and other bus masters to peripherals in a flexible manner that optimizes performance by allowing peripherals that are on different slave ports of the matrix to be accessed simultaneously by different bus masters.
Page 12 User manual 3.1 How to read this chapter K32W061/41 package is a HVQFN40 (6x6 mm). The pinout and IO cells are consistent across all product types except for the NTAG antenna connections. There are some functional differences between the IO cells used for different digital pins and these are presented in this chapter.
Page 13 UM11323 NXP Semiconductors Chapter 3: Pin and Pad Descriptions 3.3 Pinout signaling descriptions Table 3. Pin descriptions Symbol Pin Type Default at reset Description XTAL_P System crystal oscillator 32 MHz XTAL_N System crystal oscillator 32 MHz PIO0 GPIO0 GPIO0 — General Purpose digital Input/Output 0 USART0_SCK —...
Page 14 UM11323 NXP Semiconductors Chapter 3: Pin and Pad Descriptions Table 3. Pin descriptions Symbol Pin Type Default at reset Description [1][2] PIO4 GPIO4 GPIO4 — General Purpose digital Input/Output 4 SPI0_MOSI — Serial Peripheral Interface-bus 0 master output slave input PWM4 —...
Page 15 UM11323 NXP Semiconductors Chapter 3: Pin and Pad Descriptions Table 3. Pin descriptions Symbol Pin Type Default at reset Description [1][4] PIO8/TXD0 GPIO8 GPIO8 — General Purpose digital Input/Output 8 USART0_TXD — Universal Synchronous/Asynchronous Receiver/Transmitter 0 - transmit data output CT32B0_MAT0 —...
Page 16 UM11323 NXP Semiconductors Chapter 3: Pin and Pad Descriptions Table 3. Pin descriptions Symbol Pin Type Default at reset Description PIO12/SWCLK 15 SWCLK GPIO12 — General Purpose digital Input/Output 12 SWCLK — Serial Wire Debug Clock PWM0 — Pulse Width Modulator output 0 I2C1_SCL —...
Page 17 UM11323 NXP Semiconductors Chapter 3: Pin and Pad Descriptions Table 3. Pin descriptions Symbol Pin Type Default at reset Description — Supply voltage for IO PIO17/ADC3 GPIO17 ADC3 — ADC input 3 GPIO17 — General Purpose digital Input/Output 17 SPI1_MOSI — Serial Peripheral Interface-bus 1, master output slave input SWO —...
Page 18 UM11323 NXP Semiconductors Chapter 3: Pin and Pad Descriptions Table 3. Pin descriptions Symbol Pin Type Default at reset Description PIO21/ACM GPIO21 ACM — Analog Comparator Negative input GPIO21 — General Purpose digital Input/Output 21 IR_BLASTER — Infra-Red Modulator output PWM9 —...
Page 19 UM11323 NXP Semiconductors Chapter 3: Pin and Pad Descriptions Table 4. Pin properties          XTAL_P          XTAL_N PIO0 Hi-Z PIO1 Hi-Z PIO2 Hi-Z PIO3...
Page 20 UM11323 NXP Semiconductors Chapter 3: Pin and Pad Descriptions Table 4. Pin properties          DD(PMU)          XTAL_32K_P       ...
Page 21 UM11323 NXP Semiconductors Chapter 3: Pin and Pad Descriptions Table 5: Abbreviation used in the Table 4 Properties Abbreviation Descriptions Open drain enable after reset Disabled (ie reg IOCON.OD = 0) Enabled (ie reg IOCON.OD = 1) Open drain enable control...
Page 22 UM11323 NXP Semiconductors Chapter 3: Pin and Pad Descriptions Then in ACTIVE, SLEEP, DEEPSLEEP modes, user has complete control over PADs: speed, inversion, filter, open drain, pull-up, pull-down, bus keeper, disable input. These settings are configured independently of whether the pin is used as GPIO or for a specific function.
Page 23 For PIO10 and PIO11, it is necessary to configure the IO for GPIO mode in order to achieve the stated output frequencies. 3.5.3.1 IO application mode The table below lists the 40 IO application modes available on K32W061/41: Table 6. IO application mode...
Page 24 UM11323 NXP Semiconductors Chapter 3: Pin and Pad Descriptions Table 6. IO application mode IO Application mode Description of IO functional mode IOx: Strong output 0, receiver disabled, no pull-up, no pull-down, low speed IOx: Strong output 1, receiver disabled, no pull-up, no pull-down, low speed...
Page 25 UM11323 NXP Semiconductors Chapter 3: Pin and Pad Descriptions Table 6. IO application mode IO Application mode Description of IO functional mode IO with repeater mode IOx: Strong output 0, receiver enabled, pull-up enabled, pull-down enabled, low speed IOx: Strong output 0, receiver enabled, pull-up enabled, pull-down enabled, high speed...
Page 26 4.2.1 DCDC The K32W061/41 has an internal DCDC module. It is a buck converter which efficiently converts an input supply voltage to a fixed output voltage. The configuration of the DCDC module can be optimized to suit the load current of the application; there are settings for 10 mA, 20 mA, 40 mA and 60 mA.
Page 27 Chapter 4: Analog Power Management Unit 4.3 Power domains The K32W061/41 has many power domains; these are created in various ways such as internal LDOs, power switches or connections to DCDC output. The voltage of the LDOs may be changed to reduce power in certain modes and the domain may be switched off as well.
Page 28 Generally, an XTAL requires a capacitor connected between each pin of the XTAL and ground. The capacitance required is set by the specification of the crystal. The K32W061/41 has internal configurable capacitors that removes the need for external capacitors in most applications.
Page 29 UM11323 NXP Semiconductors Chapter 4: Analog Power Management Unit The software API that configures the XTAL capacitor bank setting uses this calibration data to achieve accurate operation of the XTAL. Ideally the external XTAL is stable across the whole temperature range of the device. In this case once the capacitor bank setting has been applied, it does not need modifying if the device remains powered.
Page 30 User manual 5.1 Introduction The K32W061/41 supports several low-power modes that can be used by the application to reduce average power consumption. This chapter provides an overview of these modes, what can be enabled in these modes and what events can be used to trigger a return to the normal active state.
Page 31 The device can be woken by the reset pin or an IO event unless the IOs are disabled to reduce current consumption further. For a K32W061 device, NTAG FD (Field Detect) interrupt, from the internal NTAG device can also wake up the device.
Page 32 UM11323 NXP Semiconductors Chapter 5: Power Management Table 7. Peripheral configuration in reduced power modes Peripheral Power mode Active or sleep Deep-sleep Power-down Deep power-down High speed FRO Optional FRO32K Optional Optional Optional Radio Optional On or Halted in Halted...
Page 33 UM11323 NXP Semiconductors Chapter 5: Power Management Table 8. Wake-up sources for reduced power modes Power mode Wake-up source Conditions Deep-sleep Pin interrupts Enable pin interrupts in NVIC (see more details in Chapter 9 “Nested Vectored Interrupt Controller (NVIC)”) and SYSCON_STARTER1 registers.
Page 34 UM11323 NXP Semiconductors Chapter 5: Power Management Table 8. Wake-up sources for reduced power modes Power mode Wake-up source Conditions • Deep-sleep IR modulator Enable the IR modulator • Enable IR modulator wake-up in the SYSCON_STARTER0[IRBLASTER] • SPIFI Enable the SPIFI module •...
Page 35 UM11323 NXP Semiconductors Chapter 5: Power Management Table 8. Wake-up sources for reduced power modes Power mode Wake-up source Conditions • Power-down Enable required IO to be able to cause wakeup in PMC_DPDWKSRC[PIOx] • Configure IO to be an input in GPIO_DIR[DIRP_PIOn] •...
Page 36 5.3 Functional description 5.3.1 Power management The K32W061/41 supports a variety of power control features. In Active mode, when the chip is running, power and clocks to selected peripherals can be optimized for power consumption. In addition, there are three special modes of processor power reduction with...
Page 37 UM11323 NXP Semiconductors Chapter 5: Power Management • The system clock frequency, 48 MHz to 12 MHz, and source can be selected (See Section 6.3 “Clock generation (CLK_GEN) module”). In general, the device uses less power at lower frequencies, so running the CPU and other device features at a frequency sufficient for the application (plus some margin) will save power.
Page 38 UM11323 NXP Semiconductors Chapter 5: Power Management 5.3.3.3 Wake-up from sleep mode Sleep mode is exited automatically when an interrupt enabled by the NVIC arrives at the processor or a reset occurs. After wake-up caused by an interrupt, the device returns to its original power configuration as the processor clock will be restarted and no other changes occurred due to being in sleep mode.
Page 39 UM11323 NXP Semiconductors Chapter 5: Power Management • Using an interrupt from a block such as the watchdog interrupt or RTC interrupt, when enabled during the reduced power mode via the power API. Also enable the wake-up sources in the SYSCON_STARTER registers and the NVIC.
Page 40 UM11323 NXP Semiconductors Chapter 5: Power Management 5.3.6 Deep power-down mode In deep power-down mode, power and clocks are shut off to the entire chip with the exception of the always on controllers and, if enabled, the IO cells. During deep power-down mode, the contents of the SRAM and registers are not retained.
Page 41 The CLK_GEN block has multiple input clocks that can be selected as the root clock of the system and peripheral clock outputs and respective clock trees. The following table lists the input clock sources: K32W061 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2020. All rights reserved.
Page 42 UM11323 NXP Semiconductors Chapter 6: Clock Distribution Table 9. Clock description Clock Frequency Source Description FRO_12MHz 12 MHz Derived from the 192 MHz FRO. FRO_32MHz 32 MHz Derived from the 192 MHz FRO. FRO_48MHz 48 MHz Derived from the 192 MHz FRO.
Page 43 UM11323 NXP Semiconductors Chapter 6: Clock Distribution Fig 8. 32 MHz clock sources internal muxing Fig 9. 32 kHz clock sources internal muxing All the division and/or gating features described in this chapter are provided at CLK_GEN level. Each IP block may provide additional clock control related logic, which is discussed in the related block-specific chapters.
Page 44 UM11323 NXP Semiconductors Chapter 6: Clock Distribution main_clk SYSTICKCLK SYSTICKCLK Divider to CPU SYSTICKCLKDIV[7:0], [29], [30] TRACECLK to TRACECLK debug_access Divider then CPU TRACECLKDIV[7:0], [29], [30] Fig 11. CPU SYSTICK and TRACECLK clock generation main_clk 32MHz XTAL OSC To Quad-SPIFI...
Page 45 UM11323 NXP Semiconductors Chapter 6: Clock Distribution OSC32MCLK main_clk FRO_48MHz OSC32MCLK FRG_CLK FRO_48MHz « None » « None » FRGCTRL[15:0] FRG Clock Select FRGCLKSEL[1:0] Fig 14. USART clocks selection 32MHz XTAL OSC RNG_CLK0 CLK Gating RNGCLKCTRL[0] FRO_32MHz RNG_CLK1 CLK Gating RNGCLKCTRL[0] Fig 15.
Page 46 UM11323 NXP Semiconductors Chapter 6: Clock Distribution 32MHz XTAL OSC BLE_ CLK to Bluetooth LE « None » MODEMCLKSEL[1] Fig 17. Bluetooth Low Energy clock selection main_clk 32KHz XTAL OSC FRO_32KHz 32MHz XTAL OSC CLKOUT CLKOUT Divider « None »...
Page 47 UM11323 NXP Semiconductors Chapter 6: Clock Distribution main_clk OSC32KCLK FRO_48MHz MCLK_IN DMICCLK to DMIC DMICCLK Divider FRO_1MHz FRO_12MHz DMICCLKDIV[ 7 :0], [29], [30] « None » Fig 20. DMIC clock selection The DMIC IP can receive an external clock (MCLK_IN), as shown in Figure 20 “DMIC...
Page 48 UM11323 NXP Semiconductors Chapter 6: Clock Distribution OSC32MCLK FRO_48MHz PWM CLK to PWM « None » PWM Modulator Clock Select PWMCLKSEL[1:0] Fig 22. PWM clock Fig 23. IR Blaster clock Fig 24. SPICLK selection K32W061 All information provided in this document is subject to legal disclaimers.
Page 49 UM11323 NXP Semiconductors Chapter 6: Clock Distribution Fig 25. I2C clocks Fig 26. ADC clock generation 6.3.1 Clock outputs Next table lists all the output clocks generated by the CLK_GEN module, relative sources, division factor(s) and clock gating support availability: Table 10.
Page 50 UM11323 NXP Semiconductors Chapter 6: Clock Distribution Table 10. Clock outputs Clock Source Division Gating Descriptions USART_CLK main_clk None To USART 0 and 1 OSC32M FRO48M FRGCLK RNG_CLK0 None XTAL32M RNG_CLK1 FRO32M None ZIGBEE_CLK XTAL32M BLE_CLK XTAL32M None CLKOUT main_clk...
Page 51 UM11323 NXP Semiconductors Chapter 6: Clock Distribution Table 10. Clock outputs Clock Source Division Gating Descriptions SPICLK[1:0] XTAL32M None FRO32M FRO48M CONTROLLED_FRO1MHz FRO1M None To Frequency Measure CONTROLLED_32MHz XTAL32M None To Frequency Measure XTAL_OSC Frequency and division factors restricted to the following final system clock frequencies: FRO12MHz (Default CPU boot), FRO 16MHz, FRO 24MHz, FRO 32MHz, FRO48 MHz, XTAL 32MHz, XTAL16MHz.
Page 52 UM11323 NXP Semiconductors Chapter 6: Clock Distribution 6.3.2.2 Clock selection at power-up and initialization At power-up, the hardware boot is managed by the PMC state machine. It enables the High Speed FRO, and after the power-up of analog blocks and applying trim values from efuse, it releases the CPU reset.
Page 53 UM11323 NXP Semiconductors Chapter 6: Clock Distribution Table 11. Clock sources controllable by software APIs Clock Name Description Enabled by Default? kCLOCK_Sram0 The clock for SRAM controller0, for SRAM blocks SRAM0 to SRAM7 kCLOCK_Sram1 The clock for SRAM controller1, for SRAM blocks SRAM8 to SRAM11...
Page 54 UM11323 NXP Semiconductors Chapter 6: Clock Distribution Table 11. Clock sources controllable by software APIs Clock Name Description Enabled by Default? kCLOCK_ExtClk The clock that can be sourced from PIO19 kCLOCK_WdtClk The Watchdog Timer Clock kCLOCK_Frg The Fractional Rate generator (FRG) that can be used with the USARTS...
Page 55 UM11323 Chapter 7: Reset, Boot and Wakeup Rev. 1.1 — June 2020 User manual 7.1 Introduction The K32W061/41 device is provided with the following reset sources: Table 12. Reset Reset Type Description Voltage Resets System Power-On-Reset (POR) External Resets External Pin reset (RESETN)
Page 56 UM11323 NXP Semiconductors Chapter 7: Reset, Boot and Wakeup 7.2.2.1 External Pin Reset The RESETN is a dedicated pin on this device. This pin is open drain and has an internal pull-up. Asserting RESETN wakes the device from any mode.
Page 57 UM11323 NXP Semiconductors Chapter 7: Reset, Boot and Wakeup Table 13. Reset outputs from RST_GEN Analog Digital Power on reset (POR) External pin reset Software reset Watchdog timer reset Arm system reset Wakeup IO reset Brown out detector (BOD) reset Y: Yes;...
Page 58 UM11323 NXP Semiconductors Chapter 7: Reset, Boot and Wakeup ‘1' reset_n_sync pad_reset_n PAD RESETN reset_n Reset pmc_rst_n Sync reset_n_sync wdt_reset wdt_reset_n_sync wdt_reset_ena Reset Sync reset_n_sync wakeup_io_reset wakeup_io_reset_n_sync wakeup_io_reset_ena Reset Sync reset_n_sync swr_reset [SWRESETCTRL ICRESETREQ=1 and swr_reset_n_sync VECTKEY=0x05FA] swr_reset_ena Reset Sync Fig 27.
Page 59 UM11323 NXP Semiconductors Chapter 7: Reset, Boot and Wakeup The RST_GEN receives reset requests from different sources, it combines and synchronizes them and generates the resets for most digital blocks and peripherals. The SLEEP Controller block must take over the control of CPU and peripherals resets at wake-up from power down and deep power down modes.
Page 60 UM11323 NXP Semiconductors Chapter 7: Reset, Boot and Wakeup The CPU clock defaults to 12 MHz after reset, and the boot code runs at this speed. Table 14. Boot modes Mode Flash Boot SW Actions   Hardware test Initialize flash...
Page 61 7.3.3 Boot process The following figures show the ROM's boot process of the K32W061/41. Figure 29 shows the boot sequence from a cold start.
Page 62 UM11323 NXP Semiconductors Chapter 7: Reset, Boot and Wakeup CPU out of reset Read protection settings Hardware Hardware test mode test mode requested ? allowed ? ISP allowed? requested? Read, verify Read, verify and apply and apply ROM patch trim settings...
Page 63 UM11323 NXP Semiconductors Chapter 7: Reset, Boot and Wakeup Fig 30. Boot from warm start Some details about the blocks in the previous diagrams: The protection settings are stored in the “protected data” region of the flash memory (pFlash), mapped at the address range of 9EC00 - 9EFFF. They contain the ROM patch and several device configuration data.
Page 64 UM11323 NXP Semiconductors Chapter 7: Reset, Boot and Wakeup The ISP state allows a PC-based programmer application to interact through the USART port, and request various actions. ISP can be used at several levels of access: • Unrestricted (secure or unsecure): normal developer mode •...
Page 65 Power modes are highly configurable. Some examples of the possible modes are shown in Table 15.: K32W061 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2020. All rights reserved. User manual Rev. 1.1 — June 2020...
Page 66 UM11323 NXP Semiconductors Chapter 8: Power Management Controller and SLEEPCON Table 15. Possible power modes and state of power domains Power modes Power domains Active PM_ACTIVE template PM_ACTIVE_MIN_REF PM_ACTIVE_RADIO PM_ACTIVE_SINGLE PM_ACTIVE_DUAL Sleep PM_SLEEP Modes Deep PM_DEEP_SLEEP template RET/ RET/ RET/...
Page 67 UM11323 NXP Semiconductors Chapter 8: Power Management Controller and SLEEPCON Table 16. Proposed power modes and state of analog modules Power modes Analog modules Active PM_ACTIVE template On On/ On On PM_ACTIVE_MIN_REF Off Off On Off On On PM_ACTIVE_RADIO Off Off On Off On On...
Page 68 UM11323 NXP Semiconductors Chapter 8: Power Management Controller and SLEEPCON 8.3 Low level drivers APIs The low level driver APIs provide the way for the application to request a specific power mode. The API is then responsible for performing any required configuration and sequencing to put the device into the required mode.
Page 69 Chapter 9: Nested Vectored Interrupt Controller (NVIC) Rev. 1.1 — June 2020 User manual 9.1 How to read this chapter Available interrupt sources vary slightly with specific K32W061/41 device type. A device with internal NTAG will have an additional interrupt source. 9.2 Features •...
Page 70 UM11323 NXP Semiconductors Chapter 9: Nested Vectored Interrupt Controller (NVIC) Table 17. Connection of interrupt sources to the NVIC Interrupt Interrupt source name Interrupt Handler Descriptions source number DebugMonitor_IRQn DebugMon_Handler Cortex-M4 Debug Monitor Interrupt PendSV_IRQn PendSV_Handler Cortex-M4 Pend SV Interrupt...
Page 71 UM11323 NXP Semiconductors Chapter 9: Nested Vectored Interrupt Controller (NVIC) Table 17. Connection of interrupt sources to the NVIC Interrupt Interrupt source name Interrupt Handler Descriptions source number HWVAD_IRQn HWVAD0_IRQHandler Hardware Voice activity detection interrupt BLE_DP_IRQn Bluetooth Low Energy Data Path interrupt...
Page 72 This feature is used by the boot loader and the selective OTA code; it should not be used by application code. K32W061 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2020. All rights reserved.
Page 73 UM11323 NXP Semiconductors Chapter 10: System Configuration (SYSCON) 10.3 System tick clock System tick clock is a clock sent to the CPU to serve as a reference for counting delays. Some calibration information can be provided for even better accuracy.
Page 74 UM11323 NXP Semiconductors Chapter 10: System Configuration (SYSCON) 10.5 Accessing peripherals through internal buses There are several internal buses within the IC and consequently, some bridges between these buses. It is necessary to enable async APB bridge to access async system controller (ASYNC_SYSCON) and timer modules (CTIMER0 and CTIMER1), with the ASYNCAPBCTRL register.
Page 75 UM11323 NXP Semiconductors Chapter 10: System Configuration (SYSCON) • kOSC32M_to_SPI_CLK • kFRO48M_to_SPI_CLK • kNONE_to_SPI_CLK Select one of these clock sources using CLOCK_AttachClk (kFRO48M_to_SPI_CLK); 10.7 TRNG control TRNG stands for true random number generation. Within the SYSCON module the register RNGCLKCTRL[ENABLE] enables input clocks that are used within the TRNG to generate randomness.
Page 76 UM11323 NXP Semiconductors Chapter 10: System Configuration (SYSCON) 2. Set RETENTIONCTRL[IOCLAMP] bit to enable the feature 3. Disable peripherals 4. Go to power down mode After wake-up from power-down, it is necessary to release the clamping to allow for normal operation. However, to prevent the IOs from being disturbed, it is necessary to follow this procedure: 1.
Page 77 UM11323 NXP Semiconductors Chapter 10: System Configuration (SYSCON) • Wake timer current counter values can be read – Wake timer0 value can be read through WKT_VAL_WKT0_LSB and WKT_VAL_WKT0_MSB registers – Wake timer1 value can be read through WKT_VAL_WKT1 register – When reading the wake timers, it is necessary to re-read it until a consistent value is read twice.
Page 78 When using the power management software, the user identifies the required functionality. The software then manages which power mode to use and the functional blocks that need to be active. K32W061 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2020. All rights reserved.
Page 79 Rev. 1.1 — June 2020 User manual 12.1 How to read this chapter The IOCON block is included on all K32W061/41 parts. Registers for pins that are not available on a specific package are reserved. K32W061/41 package is a HVQFN40 (6x6 mm).
Page 80 UM11323 NXP Semiconductors Chapter 12: I/O Pin Configuration (IOCON) 12.4 General description 12.4.1 Pin configuration open-drain enable strong output enable pull-up pin configured data output as digital output strong pull-down weak pull-up pull-up enable repeater weak mode enable pull-down pull-down enable...
Page 81 UM11323 NXP Semiconductors Chapter 12: I/O Pin Configuration (IOCON) Multiple connections Since a particular peripheral function may be allowed on more than one pin, it is possible to configure more than one pin to perform the same function. If a peripheral output function is configured on more than one pin, it will be routed to those pins.
Page 82 xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx Table 19. IOMUX functions Value of FUNC field in PIOn registers Register Default at Default Max.
Page 83 xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx Table 19. IOMUX functions …continued Value of FUNC field in PIOn registers Register Default at Default Max.
Page 84 UM11323 NXP Semiconductors Chapter 12: I/O Pin Configuration (IOCON) 12.4.2.2 Pin configuration The IO cells for PIO0_0 to PIO0_21 can all be configured for digital operation. To support analog functionality, such as ADC inputs, they can also be configured in analog mode.
Page 85 UM11323 NXP Semiconductors Chapter 12: I/O Pin Configuration (IOCON) enabled. This protects the analog input from voltages outside the range of the analog power supply and reference that may sometimes be present on digital pins, since they are typically 3.6 V tolerant. All pin types include this control, even if they do not support any analog functions.
Page 86 UM11323 NXP Semiconductors Chapter 12: I/O Pin Configuration (IOCON) This function is used to associate a multiple pins to a peripheral. The following values are available: • IOCON_FUNC0 to IOCON_FUNC7: Selects the pin function to a value between 0 and 7 •...
Page 87 Chapter 13: Input Multiplexing (INPUTMUX) Rev. 1.1 — June 2020 User manual 13.1 How to read this chapter Input multiplexing is present on all K32W061/41 devices. 13.2 Features • Configure the inputs to the pin interrupt block and pattern match engine.
Page 88 Each of the pin interrupts must be enabled in the NVIC before it becomes active. In K32W061/41, only pin interrupt 0 to 3 is connected to the NVIC. To use the selected pins for pin interrupts or the pattern match engine, see Chapter 15 “Pin Interrupt and Pattern Match (PINT)”...
Page 89 UM11323 NXP Semiconductors Chapter 13: Input Multiplexing (INPUTMUX) • PIO0_0 is connected to PINTSEL0  PINTSEL0->INTPIN[4:0] = 0x0 • PIO0_2 is connected to PINTSEL1  PINTSEL1->INTPIN[4:0] = 0x2 • PIO0_5 is connected to PINTSEL2  PINTSEL2->INTPIN[4:0] = 0x5 • PIO0_8 is connected to PINTSEL3  PINTSEL3->INTPIN[4:0] = 0x8 •...
Page 90 UM11323 NXP Semiconductors Chapter 13: Input Multiplexing (INPUTMUX) Table 22. DMA trigger Input mux registers (DMA_ITRIG_INMUXn (n = 0-18), offsets [0xE0:0x128]) bit description Symbol Descriptions Reset Value Trigger input number (decimal value) for DMA channel 0x1F n (n = 0 to 17).
Page 91 The state of a selected subset of the pins can be read from a Masked Pin (MPIN) register. Pins having a 1 in the Mask register will read as 0 from its MPIN register. K32W061 All information provided in this document is subject to legal disclaimers.
Page 92 UM11323 NXP Semiconductors Chapter 14: General Purpose I/O (GPIO) 14.5.2 GPIO output Each GPIO pin has an output bit in the GPIO block. These output bits are the targets of write operations to the pins. Two conditions must be met in order for a pin’s output bit to be driven onto the pin: 1.
Page 93 UM11323 NXP Semiconductors Chapter 14: General Purpose I/O (GPIO) 14.5.4 GPIO direction Each GPIO pin can be configured as input or output using the DIR register. The direction of individual pins can be set, cleared, or toggled using the DIRSET, DIRCLR, and DIRNOT registers.
Page 94 Chapter 15: Pin Interrupt and Pattern Match (PINT) Rev. 1.1 — June 2020 User manual 15.1 How to read this chapter The pin interrupt generator and the pattern match engine are available on all K32W061/41 parts. 15.2 Features This block has two mutually exclusive features: •...
Page 95 UM11323 NXP Semiconductors Chapter 15: Pin Interrupt and Pattern Match (PINT) – Pin interrupts 0 to 3 are assigned to an interrupt in the NVIC (Table 17 “Connection of interrupt sources to the NVIC”). Interrupt 4 to 7 are not supported in this processor.
Page 96 UM11323 NXP Semiconductors Chapter 15: Pin Interrupt and Pattern Match (PINT) Fig 35. Pattern Match Engine 15.3.1 Configure pins as pin interrupts or as inputs to the pattern match engine Follow these steps to configure pins as pin interrupts: 1. Determine which digital pins are required for the pin interrupt or pattern match function.
Page 97 UM11323 NXP Semiconductors Chapter 15: Pin Interrupt and Pattern Match (PINT) 15.5 General description Pins with configurable functions can serve as external interrupts or inputs to the pattern match engine. Up to eight pins can be configured using the INPUTMUX_PINTSEL registers for these features.
Page 98 UM11323 NXP Semiconductors Chapter 15: Pin Interrupt and Pattern Match (PINT) to IN7 slice n - 1 from slice n -1 to IN0 (tied HIGH for slice 0) slice n - 1 INPUT MUX slice n endpoint configured? PMCFG bit n = 1...
Page 99 UM11323 NXP Semiconductors Chapter 15: Pin Interrupt and Pattern Match (PINT) The pattern match module is constructed of eight bit-slice elements. Each bit slice is programmed to represent one component of one minterm (product term) within the boolean expression. The interrupt request associated with the last bit slice for a particular minterm will be asserted whenever that minterm is matched (only for the 4 first minterms).
Page 100 UM11323 NXP Semiconductors Chapter 15: Pin Interrupt and Pattern Match (PINT) • The ORed result of all three minterms asserts the RXEV request to the CPU. That is, if any of the three terms are true, the output is asserted.
Page 101 UM11323 NXP Semiconductors Chapter 15: Pin Interrupt and Pattern Match (PINT) – SRC4: 011 - select input 3 for bit slice 4 – SRC5: 110 - select input 6 for bit slice 5 – SRC6: 101 - select input 5 for bit slice 6 –...
Page 102 UM11323 NXP Semiconductors Chapter 15: Pin Interrupt and Pattern Match (PINT) 15.6.3 Pattern match engine edge detect examples system clock slice 0 (IN0re) SRC0 = 0, CFG0 = 0x3, PROD_ENDPTS0 = 0x0 (sticky rising edge detection) slice 1 (IN1ev) minterm...
Page 103 UM11323 NXP Semiconductors Chapter 15: Pin Interrupt and Pattern Match (PINT) system clock slice 0 (IN0) SRC0 = 0, CFG0 = 0x4, PROD_ENDPTS0 = 0x0 (high level detection) slice 1 (IN1ev) minterm (IN0)(IN1ev) no pin interrupt raised IN1 does not change while...
Page 104 The group interrupt allows a specified subset of the available inputs to generate one single interrupt request, either when any one of the enabled inputs K32W061 All information provided in this document is subject to legal disclaimers.
Page 105 UM11323 NXP Semiconductors Chapter 16: Group GPIO Input Interrupt (GINT) is active or when all of the enabled inputs are active. It cannot, however, respond to AND/OR Boolean expressions. The pattern matching function (PINT) can be used to specify complex AND/OR Boolean expressions and can generate multiple, separate interrupt requests for each AND term within the expression.
Page 106 UM11323 NXP Semiconductors Chapter 16: Group GPIO Input Interrupt (GINT) Fig 41. GINT Example for “(IO0 asserted) OR (IO2 asserted) OR (IO4 asserted) “ 16.5.2 Example 2 The following example shows some example waveforms input into the GINT block. For the GINT configuration specified here it is shown when interrupts would be generated.
Page 107 Chapter 17: Direct Memory Access (DMA) Rev. 1.1 — June 2020 User manual 17.1 How to read this chapter The DMA controller is available on all K32W061/41 devices. 17.2 Features • 19 channels which are connected to peripheral DMA requests. These come from the...
Page 108 UM11323 NXP Semiconductors Chapter 17: Direct Memory Access (DMA) 17.4 Pin description The DMA controller has no direct pin connections. However, some DMA triggers can be associated with pin functions (see Section 17.5.1.2). 17.5 General description DMA request clears DMA_OTRIG_INMUXn...
Page 109 UM11323 NXP Semiconductors Chapter 17: Direct Memory Access (DMA) request is likely to require transferring several non-contiguous result registers at once (see Chapter 27 “12-bit ADC Controller (ADC)”). It might also require other things to be done that can be done by the DMA without software intervention. This model fits better with the trigger facility, so that is how the ADC is connected to the DMA controller.
Page 110 UM11323 NXP Semiconductors Chapter 17: Direct Memory Access (DMA) 17.5.1.1.1 DMA with I C monitor mode The I C monitor function may be used with DMA if one of the channels related to the same C Interface is available. Table 26.
Page 111 UM11323 NXP Semiconductors Chapter 17: Direct Memory Access (DMA) 17.5.2 DMA Modes The DMA controller doesn’t really have separate operating modes, but there are ways of using the DMA controller that have commonly used terminology in the industry. Once the DMA controller is set up for operation, using any specific DMA channel requires...
Page 112 UM11323 NXP Semiconductors Chapter 17: Direct Memory Access (DMA) Table 29: Channel descriptor for a single transfer Offset Description + 0x0 Reserved + 0x4 Source data end address + 0x8 Destination data end address + 0xC (not used) This case is identified by the XFERCFGn[RELOAD] = 0. When the DMA channel receives a DMA request or trigger (depending on how it is configured), it performs one or more transfers as configured, then stops.
Page 113 UM11323 NXP Semiconductors Chapter 17: Direct Memory Access (DMA) The reverse of this process could be done using XFERCFGn[DSTINC] to de-interleave combined data from the buffer and send it to several peripherals or locations. Buffer start Entry 0, first pass...
Page 114 UM11323 NXP Semiconductors Chapter 17: Direct Memory Access (DMA) – If channel x is configured to auto reload the descriptor on exhausting of the descriptor (XFERCFGn[RELOAD] is set), then enable 'clear trigger on descriptor exhausted' by setting bit XFERCFGn[CLRTRIG]. •...
Page 115 UM11323 NXP Semiconductors Chapter 17: Direct Memory Access (DMA) 17.6.3 SRAM Base address register The DMA function uses a DMA descriptor table which is located in SRAM. The SRAMBASE register must be configured with an address where DMA descriptors will be stored.
Page 116 UM11323 NXP Semiconductors Chapter 17: Direct Memory Access (DMA) 17.6.6 Active status register The ACTIVE0 register indicates which DMA channels are active at the point when the read occurs. The register is read-only. A DMA channel is considered active when a DMA operation has been started but not yet fully completed.
Page 117 UM11323 NXP Semiconductors Chapter 17: Direct Memory Access (DMA) 17.6.12 Interrupt B register The INTB0 register contains the interrupt B status for each DMA channel. The status will be set when the SETINTB bit is 1 in the transfer configuration for a channel, when the descriptor becomes exhausted.
Page 118 UM11323 NXP Semiconductors Chapter 17: Direct Memory Access (DMA) • SRCBURSTWRAP: configure whether the source address range for each burst is the same • DSTBURSTWRAP: configure whether the source address range for each burst is the same • CHPRIORITY: configure channel priority...
Page 119 UM11323 NXP Semiconductors Chapter 17: Direct Memory Access (DMA) • SWTRIG: Used to trigger the DMA channel by SW • CLRTRIG: Controls if trigger is cleared when the descriptor is exhausted • SETINTA: control if INTA flag is set when the descriptor is exhausted •...
Page 120 Chapter 18: Pulse Width Modulation (PWM) Rev. 1.1 — June 2020 User manual 18.1 How to read this chapter The PWM is available on all K32W061/41 devices. 18.2 Features The features of the PWM are: • Ten 16-bit auto reload down counters •...
Page 121 UM11323 NXP Semiconductors Chapter 18: Pulse Width Modulation (PWM) 18.4 Pin description Chapter 12 “I/O Pin Configuration (IOCON)” to assign PWM functions to external pins. Two of the PWM channels, PWM8 and PWM9, can be used as a trigger for the ADC SEQ controller.
Page 122 UM11323 NXP Semiconductors Chapter 18: Pulse Width Modulation (PWM) Fig 45. PWM Architecture K32W061 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2020. All rights reserved. User manual Rev. 1.1 — June 2020 122 of 350...
Page 123 UM11323 NXP Semiconductors Chapter 18: Pulse Width Modulation (PWM) 18.6 Functional description 18.6.1 Prescaler There are eleven 10-bit prescalers. The frequency of the scaled clock enable is calculated as follows. / (pscl +1) scaled Where F is the frequency of the AHB clock, pscl is the prescaler setting for the PWM channel.
Page 124 UM11323 NXP Semiconductors Chapter 18: Pulse Width Modulation (PWM) Fig 47. PWM Waveform 18.6.4 Interrupt generator There are eleven overflow interrupts which connect directly to the NVIC interface of the MCU. There interrupts can be read from the PWM status registers PST0 to PST2.
Page 125 UM11323 NXP Semiconductors Chapter 18: Pulse Width Modulation (PWM) 18.7 Software control To use the functionality of the PWM module it is recommended to use software functions from within fsl_pwm.c. K32W061 All information provided in this document is subject to legal disclaimers.
Page 126 Chapter 19: Standard Counter/Timers (CT32B) Rev. 1.1 — June 2020 User manual 19.1 How to read this chapter These two standard timers are available on all K32W061/41 devices. 19.2 Features • Each is a 32-bit counter/timer with a programmable 32-bit prescaler. Both of the timers include two capture and two match pin connections.
Page 127 UM11323 NXP Semiconductors Chapter 19: Standard Counter/Timers (CT32B) • DMA: Some timer match conditions can be used to generate timed DMA requests, Table 25 “DMA requests & trigger muxes”. 19.4 Applications • Interval Timer for counting internal events. • PWM outputs •...
Page 128 UM11323 NXP Semiconductors Chapter 19: Standard Counter/Timers (CT32B) 161220 Match reload registers 0 to 3 Match registers 0 to 3 Match Control register External Match register Interrupt register Control MAT[1:0] Interrupt Compare DMA request CAP[1:0] Stop on match Reset on match...
Page 129 UM11323 NXP Semiconductors Chapter 19: Standard Counter/Timers (CT32B) Table 34. Timer/Counter pin description Type Description CTIMER0_CAP1:0 Input Capture Signals- A transition on a capture pin can be configured to load one of the Capture CTIMER1_CAP1:0 Registers with the value in the Timer Counter and optionally generate an interrupt.
Page 130 UM11323 NXP Semiconductors Chapter 19: Standard Counter/Timers (CT32B) Table 37: Suggested CTIMER pin setting for combo IO cells (PIO10 and PIO11) IOCON Field Setting Comment bit(s) Invert No need to invert Digimode Digital mode FilterOff Generally disable filter Fsel Not valid for GPIO mode...
Page 131 UM11323 NXP Semiconductors Chapter 19: Standard Counter/Timers (CT32B) 19.7.1 Rules for single edge controlled PWM outputs 1. All single edge controlled PWM outputs go LOW at the beginning of each PWM cycle (timer is set to zero) unless their match value is equal to zero.
Page 132 UM11323 NXP Semiconductors Chapter 19: Standard Counter/Timers (CT32B) Note: Because timer DMA requests are generated whenever the timer value is equal to the related Match Register value, DMA requests are always generated when the timer is running, unless the Match Register value is higher than the upper count limit of the timer.
Page 133 Chapter 20: Windowed Watchdog Timer (WWDT) Rev. 1.2 — June 2020 User manual 20.1 How to read this chapter The watchdog timer is available on all K32W061/41 devices. 20.2 Features • Internally resets chip if not reloaded during the programmable time-out period.
Page 134 UM11323 NXP Semiconductors Chapter 20: Windowed Watchdog Timer (WWDT) SYSCON Windowed Watchdog Timer system clock WWDT registers SYSAHBCLKCTRL0 (WWDT clock enable) 6 kHz to 1.5 MHz watchdog oscillator TV: 24-bit timer PDRUNCFG 170315 Fig 52. WWDT clocking 20.4 Pin description The WWDT has no external pins.
Page 135 UM11323 NXP Semiconductors Chapter 20: Windowed Watchdog Timer (WWDT) • The Watchdog must be fed again before the Watchdog counter reaches zero in order to prevent a watchdog event. If a window value is programmed, the feed must also occur after the watchdog counter passes that value.
Page 136 UM11323 NXP Semiconductors Chapter 20: Windowed Watchdog Timer (WWDT) 20.5.2 Clocking and power control The watchdog timer block uses two clocks: APB bus clock and WDCLK. The APB bus clock is used for the APB accesses to the watchdog registers and is derived from the...
Page 137 UM11323 NXP Semiconductors Chapter 20: Windowed Watchdog Timer (WWDT) WDCLK / 4 Watchdog 1201 1200 11FF 11FE 11FD 11FC 2000 1FFF 1FFE 1FFD 1FFC Counter Correct Feed Event Watchdog Reset Conditions: WINDOW = 0x1200 WARNINT = 0x3FF = 0x2000 Fig 55. Correct watchdog feed with windowed mode enabled...
Page 138 UM11323 NXP Semiconductors Chapter 20: Windowed Watchdog Timer (WWDT) Table 38. Watchdog operating modes selection WDEN WDRESET Mode of operation X (0 or 1) Debug/Operate without the Watchdog running. Watchdog interrupt mode: the watchdog warning interrupt will be generated but watchdog reset will not.
Page 139 Chapter 21: Real-Time Clock (RTC) Rev. 1.1 — June 2020 User manual 21.1 How to read this chapter The RTC is available on all K32W061/41 devices. 21.2 Features • The RTC is driven by either the 32K FRO or XTAL •...
Page 140 UM11323 NXP Semiconductors Chapter 21: Real-Time Clock (RTC) Fig 57. RTC clocking 21.3.1 RTC timers The RTC contains two timers: 1. The main RTC timer. This 32-bit timer uses a 1 Hz clock and is intended to run continuously as a real-time clock. When the timer value reaches a match value, an interrupt is raised.
Page 141 UM11323 NXP Semiconductors Chapter 21: Real-Time Clock (RTC) minimum interval afforded by the main RTC counter. For these applications, a higher frequency secondary timer has been provided. This secondary timer is an independent, stand-alone wake-up or general-purpose timer for timing intervals of up to 64 seconds with approximately one millisecond of resolution.
Page 142 Rev. 1.1 — June 2020 User manual 22.1 How to read this chapter The system tick timer (SysTick timer) is present on all K32W061/41 devices. Refer to “Cortex-M4 TRM” for full details of the functionality and registers of this block. 22.2 Basic configuration Configuration of the system tick timer is accomplished as follows: 1.
Page 143 UM11323 NXP Semiconductors Chapter 22: CPU System Tick Timer (SYSTICK) Fig 58. System tick timer block diagram The SysTick timer is an integral part of the Cortex-M4. The SysTick timer is used to generate a fixed 10 ms interrupt for use by an operating system or other system management software.
Page 144 UM11323 NXP Semiconductors Chapter 22: CPU System Tick Timer (SYSTICK) 22.5 Functional description The SysTick timer is a 24-bit timer that counts down to zero and generates an interrupt. The intent is to provide a fixed 10 millisecond time interval between interrupts. The...
Page 145 UM11323 NXP Semiconductors Chapter 22: CPU System Tick Timer (SYSTICK) Program the SYST_CSR register with the value 0x7 which selects the system clock as the clock source and enables the SysTick timer and the SysTick timer interrupt. In this case the system clock is derived from the FRO 12 MHz clock.
Page 146 Receiver/Transmitter (USART) Rev. 1.1 — June 2020 User manual 23.1 How to read this chapter Two USART functions are available on all K32W061/41 devices. 23.2 Features • 7, 8, or 9 data bits and 1 or 2 stop bits. •...
Page 147 UM11323 NXP Semiconductors Chapter 23: Universal Synchronous/Asynchronous Receiver/Transmitter (USART) • Enable the USART function by writing to the PSELID register of the related USART Interface. • Configure the FIFOs for operation. • Configure USART for receiving and transmitting data: – In the SYSCON_AHBCLKCTRL1 register, set the appropriate bit for the related USART Interface in order to enable the clock to the register interface.
Page 148 UM11323 NXP Semiconductors Chapter 23: Universal Synchronous/Asynchronous Receiver/Transmitter (USART) 23.3.2 Configure the USART for wake-up A USART can wake up the system from sleep mode in asynchronous or synchronous mode on any enabled USART interrupt. In deep-sleep mode, there are two options for configuring USART for wake-up: •...
Page 149 UM11323 NXP Semiconductors Chapter 23: Universal Synchronous/Asynchronous Receiver/Transmitter (USART) • The USART wakes up the part from power down mode on all events that cause an interrupt and are enabled. Typical wake-up events are: – A start bit is received.
Page 150 UM11323 NXP Semiconductors Chapter 23: Universal Synchronous/Asynchronous Receiver/Transmitter (USART) Table 40: Suggested USART pin setting for standard GPIO IO IOCON bit(s) Field Setting Note FilterOff Generally disable filter Slew1 With slew0: generally set to 0. Settings to 1,2 or 3 at...
Page 151 UM11323 NXP Semiconductors Chapter 23: Universal Synchronous/Asynchronous Receiver/Transmitter (USART) The Baud Rate Generator block divides the incoming clock to create an oversample clock (typically 16x) in the standard asynchronous operating mode. The BRG clock input source is the shared Fractional Rate Generator that runs from the USART function clock. The 32 kHz operating mode generates a specially timed internal clock based on the RTC oscillator frequency.
Page 152 UM11323 NXP Semiconductors Chapter 23: Universal Synchronous/Asynchronous Receiver/Transmitter (USART) 23.6.2 Clocking and baud rates In order to use the USART, clocking details must be defined such as setting up the clock source selection, the BRG, and setting up the FRG if it is the selected clock source.
Page 153 UM11323 NXP Semiconductors Chapter 23: Universal Synchronous/Asynchronous Receiver/Transmitter (USART) 23.6.2.3 32 kHz mode In order to use a 32 kHz clock to operate a USART at any reasonable speed, a number of adaptations need to be made. First, 16x overclocking has to be abandoned. Otherwise, the maximum data rate would be very low.
Page 154 UM11323 NXP Semiconductors Chapter 23: Universal Synchronous/Asynchronous Receiver/Transmitter (USART) Figure 60 shows an overview of RTS and CTS within the USART. Fig 60. Hardware flow control using RTS and CTS 23.6.5.2 Software flow control Software flow control could include XON / XOFF flow control, or other mechanisms. these...
Page 155 UM11323 NXP Semiconductors Chapter 23: Universal Synchronous/Asynchronous Receiver/Transmitter (USART) 23.6.7 RS-485 support RS-485 support requires some form of address recognition and data direction control. This USART has provisions for hardware address recognition (see the CFG[AUTOADDR] and the ADDR register), as well as software address recognition (see the CTL[ADDRDET] bit).
Page 156 UM11323 NXP Semiconductors Chapter 23: Universal Synchronous/Asynchronous Receiver/Transmitter (USART) 23.6.10 LIN bus The only difference between standard operation and LIN mode is that LIN mode alters the way that break generation and detection is performed (see Section 23.6.9 for details of the standard break).
Page 157 UM11323 Chapter 24: Serial Peripheral Interfaces (SPI) Rev. 1.1 — June 2020 User manual 24.1 How to read this chapter Two SPI functions (SPI0 and SPI1) are available on all K32W061/41 devices. 24.2 Features • Master and slave operation. •...
Page 158 UM11323 NXP Semiconductors Chapter 24: Serial Peripheral Interfaces (SPI) 24.3.1 Configure the SPI for wake-up In sleep mode, any signal that triggers an SPI interrupt can wake the part, provided that the interrupt is enabled in the INTENSET register and the NVIC. As long as the SPI clock is configured to be active in sleep mode, the SPI can wake up the part independently of whether the SPI block is configured in master or slave mode.
Page 159 UM11323 NXP Semiconductors Chapter 24: Serial Peripheral Interfaces (SPI) Table 42: SPI Pin Description Function Type Pin name used in Pin Description Description chapter SPIn_SCK Serial Clock for SPI on SPI Interface n. SCK is a clock signal used to synchronize the transfer of data.
Page 160 UM11323 NXP Semiconductors Chapter 24: Serial Peripheral Interfaces (SPI) Table 44: Suggested SPI pin settings IOCON Standard IO pin GPIO10 or 11 bit (s) Name Setting Name Setting   IO_CLAMP Set to 0, normal operation IO_CLAMP Set to 0, normal operation...
Page 161 UM11323 NXP Semiconductors Chapter 24: Serial Peripheral Interfaces (SPI) 24.5 General description Fig 61. SPI block diagram 24.6 Functional description 24.6.1 AHB bus access With the exception of the FIFOWR register, the bus interface to the SPI registers contained in the SPI Interface support only word writes. Byte and halfword writes are not supported in conjunction with the SPI function for those registers.
Page 162 UM11323 NXP Semiconductors Chapter 24: Serial Peripheral Interfaces (SPI) 24.6.2 Operating modes: clock and phase selection SPI interfaces typically allow configuration of clock phase and polarity. These are sometimes referred to as numbered SPI modes, as described in Table 45...
Page 163 UM11323 NXP Semiconductors Chapter 24: Serial Peripheral Interfaces (SPI) 24.6.3 Frame delays Several delays can be specified for SPI frames. These include: • Pre_delay: delay after SSEL is asserted before data clocking begins • Post_delay: delay at the end of a data frame before SSEL is deasserted •...
Page 164 UM11323 NXP Semiconductors Chapter 24: Serial Peripheral Interfaces (SPI) 24.6.3.2 Frame_delay The Frame_delay value controls the amount of time at the end of each frame. This delay is inserted when the TXCTL[EOFR] = 1. Frame_delay is illustrated by the examples in Figure 64.
Page 165 UM11323 NXP Semiconductors Chapter 24: Serial Peripheral Interfaces (SPI) Transfer delay: Transfer_delay = 1, Pre_delay = 0, Post_delay = 0 SCK (CPOL = 0) SCK (CPOL = 1) SSEL MOSI MISO First data frame Transfer _delay Second data frame Transfer delay: Transfer_delay = 1, Pre_delay = 0, Post_delay = 0...
Page 166 UM11323 NXP Semiconductors Chapter 24: Serial Peripheral Interfaces (SPI) The SPI clock divider is an integer divider. The SPI in master mode can be set to run at the same speed as the selected SPICLK, or at lower integer divide rates. The SPI rate will be = SPICLK/ DIVVAL.
Page 167 UM11323 NXP Semiconductors Chapter 24: Serial Peripheral Interfaces (SPI) The transfer would be started by setting the control bits and then initiating the DMA transfer of all but the last byte/halfword of data. The DMA completion interrupt function must modify the control bits to set FIFOWR[EOT] and then set-up DMA to send the last data.
Page 168 UM11323 NXP Semiconductors Chapter 24: Serial Peripheral Interfaces (SPI) A stall for Master receive can happen when a FIFO overflow (see FIFOSTAT[RXERR]) would otherwise occur if the transmitter was not stalled. In modes 0 and 2, this occurs if the FIFO is full when the next piece of data is received. This stall happens one clock edge earlier than the transmitter stall.
Page 169 UM11323 NXP Semiconductors Chapter 24: Serial Peripheral Interfaces (SPI) Transmitter stall: CPHA = 0, Frame_delay = 0, Pre_delay = 0, Post_delay = 0, 2 clock stall Mode 0 (CPOL = 0) Mode 2 (CPOL = 1) MOSI MISO First data frame...
Page 170 25.1 How to read this chapter Two I C functions (I C0 and I C1) are available on all K32W061/41 devices. Additionally, on the K32W061 device a further I C interface (I C2) is provided to interface to the internal NTAG device.
Page 171 UM11323 NXP Semiconductors Chapter 25: Inter-Integrated Circuit (I Table 47. C bus pin assignments Possible Pin Assignment I2C0_SCL PIO0_10 PIO0_15 I2C0_SDA PIO0_11 PIO0_16 I2C1_SCL PIO0_6 PIO0_12 I2C1_SDA PIO0_7 PIO0_13 I2C2_SCL Internal connection I2C2_SDA Internal connection Dedicated I2C IO cells Table 48:...
Page 172 UM11323 NXP Semiconductors Chapter 25: Inter-Integrated Circuit (I – Configure the related I C Interface pin functions via IOCON, see Chapter 12 “I/O Pin Configuration (IOCON)”. – Configure the I C clock and data rate. This includes the CLKDIV register for both master and slave modes, and MSTTIME register for master mode.
Page 173 UM11323 NXP Semiconductors Chapter 25: Inter-Integrated Circuit (I 6. Wait for the pending status to be set (STAT[MSTPENDING] = 1) by polling the STAT register. 7. Stop the transmission by setting the MSTCTL[MSTSTOP] bit to 1. 8. Wait for the pending status to be set (STAT[MSTPENDING] = 1) by polling the STAT register.
Page 174 UM11323 NXP Semiconductors Chapter 25: Inter-Integrated Circuit (I 1. Wait for the pending status to be set (SLVPENDING = 1) by polling the STAT register. Check the STAT[SLVSTATE] is indicating ADDR. If not then an error has occurred. 2. Acknowledge (“ack”) the address by setting SLVCTL[SLVCONTINUE] = 1 in the slave control register.
Page 175 UM11323 NXP Semiconductors Chapter 25: Inter-Integrated Circuit (I – Master pending – Change to idle state – Start/stop error – Slave pending – Address match (in slave mode) – Data available/ready 25.4.3.2 Wake-up from deep-sleep mode • Enable the I C interrupt in the NVIC.
Page 176 UM11323 NXP Semiconductors Chapter 25: Inter-Integrated Circuit (I Monitor function Timing C master generation SCL & function output DMA requests Control & logic Status Interrupt requests C slave function I2Cn_SDA Timeout I2Cn_SCL 160809 Fig 67. I C block diagram 25.6 Functional description 25.6.1 AHB bus access...
Page 177 UM11323 NXP Semiconductors Chapter 25: Inter-Integrated Circuit (I Nominal SCL rate = I2CCLK function clock rate / (SCL high time + SCL low time) Remark: DIVVAL must be ≥ 1. Remark: For 400 kHz clock rate, the clock frequency after the I C divider (divval) must be ≤...
Page 178 UM11323 NXP Semiconductors Chapter 25: Inter-Integrated Circuit (I 25.6.2.2.1 High-speed mode support High-speed mode requires different pin filtering, somewhat different timing, and a different drive strength on SCL for the master function. The changes needed for the handling of the...
Page 179 UM11323 NXP Semiconductors Chapter 25: Inter-Integrated Circuit (I 25.6.3 Time-out A time-out feature on an I C interface can be used to detect a “stuck” bus and potentially do something to alleviate the condition. Two different types of time-out are supported.
Page 180 UM11323 NXP Semiconductors Chapter 25: Inter-Integrated Circuit (I slave address matching or the slave address qualified feature, see Section 25.6.4 “Slave addresses”. In the case of Slave Receiver mode, data is received in the normal fashion after software matches the first data byte to the remaining portion of the 10-bit address.
Page 181 UM11323 NXP Semiconductors Chapter 25: Inter-Integrated Circuit (I • Software causes a slave address with write command to be sent and checks that the address was acknowledged. • Software turns on DMA mode in the I • DMA transfers data and eventually completes the transfer.
Page 182 UM11323 NXP Semiconductors Chapter 25: Inter-Integrated Circuit (I SLVCTL[AUTOMATCHREAD], and the SLVADR0[AUTONACK]. Table 50 shows how these controls may be used. These cases apply when an address matching SLVADR0, qualified by SLVQUAL0, is received. Table 50: Automatic operation cases Conditions:...
Page 183 UM11323 NXP Semiconductors Chapter 25: Inter-Integrated Circuit (I Table 52. Slave function state codes (SLVSTATE) Master state Descriptions Actions allowed SLVST_ADDR Address plus R/W received. At least one Software can further check the address if of the 4 slave addresses has been...
Page 184 Rev. 1.1 — June 2020 User manual 26.1 How to read this chapter The DMIC subsystem, including the dual-channel digital PDM microphone interface (DMIC) and hardware voice activity detector (HWVAD), is available on all K32W061/41 parts. 26.2 Features • DMIC (dual/stereo digital microphone interface) –...
Page 185 UM11323 NXP Semiconductors Chapter 26: Digital Microphone Interface (DMIC) – Set up the internal clock dividers for the PDM channels used via the DIVHFCLK0/1 registers. – If interrupts will be used with this peripheral, enable them in the NVIC. See Chapter –...
Page 186 UM11323 NXP Semiconductors Chapter 26: Digital Microphone Interface (DMIC) Table 54: Suggested DMIC pin setting for standard GPIO pin IOCON Field name Setting Comment bit(s) MODE No Pull-up or Pull-down FUNC Must select the correct function for this peripheral, see Table 19 “IOMUX functions”...
Page 187 UM11323 NXP Semiconductors Chapter 26: Digital Microphone Interface (DMIC) PDM_CLK0 clock D-MIC channel 0 PDM_DATA0 data PDM_DATA1 data D-MIC channel 1 PDM_CLK1 clock 160614 IOCFG[CLK_BYPASS0] = 0; IOCFG[CLK_BYPASS1] = 0; IOCFG[STEREO_DATA0] = 0 Fig 69. Typical connection to two independent microphones...
Page 188 UM11323 NXP Semiconductors Chapter 26: Digital Microphone Interface (DMIC) PDM_CLK0 select PDM_DATA0 select PDM_CLK1 PDM_DATA1 Microphone data available to external master Driven by external master while in bypass mode 150414 IOCFG[CLK_BYPASS0] = 1 Fig 72. Bypass mode with an external device taking over microphone access 26.5 General description...
Page 189 UM11323 NXP Semiconductors Chapter 26: Digital Microphone Interface (DMIC) 26.6 Functional description 26.6.1 HWVAD The hardware voice activity detector (HWVAD) analyses the PCM data from DMIC channel 0 by means of a filter block. Both the noise floor and the signal wave are examined and result in separate filter outputs.
Page 190 UM11323 NXP Semiconductors Chapter 26: Digital Microphone Interface (DMIC) With bit HWVADRSTT[RSTT], all filters can be reset. After this reset, the HWVAD filters need to converge, so for the first few milliseconds the result is not reliable. The HWVAD interrupt should be masked on NVIV level during this time frame. The wait period depends on the sample rate of the incoming data, at 1 MHz DMIC sample rate, the filters need about 2 ms to converge, for 800 kHz the period is 2.5 ms.
Page 191 UM11323 NXP Semiconductors Chapter 26: Digital Microphone Interface (DMIC) 26.6.1.2.1 Input gain setting The 24-bit PCM input signal can be shifted left or right with the gain setting in the register HWVADGAIN. This increases or decreases the volume of the input signal for the HWVAD processing.
Page 192 UM11323 NXP Semiconductors Chapter 26: Digital Microphone Interface (DMIC) 4 FS 2 FS 1 FS Half band Half band capture filter filter decimator filter filter decimator data block FIFO interface filter DC_CTRL USE2FS to I2S of Flexcomm Interface to HWVAD (DMIC channel 0 only) Fig 77.
Page 193 UM11323 NXP Semiconductors Chapter 26: Digital Microphone Interface (DMIC) However, for power consumption reasons, it is preferable that the division to the required DMIC clock be done outside of the DMIC interface block (for example using register SYSCON_DMICCLKDIV). The DMIC peripheral block is designed to run at a DMIC clock speed no faster than 6.144 MHz and with an input frequency no faster than 4 * 6.144 MHz = 24.576 MHz.
Page 194 UM11323 NXP Semiconductors Chapter 26: Digital Microphone Interface (DMIC) sample rate 4 FS 2 FS 1 FS CIC filter Half band Half band decimator decimator filter filter filter : OSR block filter 2 FS PCM 151217 Fig 79. Principle structure of the PDM to PCM conversion To achieve lower power consumption, the DC filter can be supplied with the 2FS instead of the 1FS signal, bypassing the second half band decimator filter.
Page 195 UM11323 NXP Semiconductors Chapter 26: Digital Microphone Interface (DMIC) Fig 80. Pre-emphasis filter quantized response at 96 kHz 26.6.2.3 FIFO and DMA operation SRAM Software Voice chunk buffer processing 24-bit 16 x 24-bit PCM DMIC FIFO 1 FS or 2 FS...
Page 196 UM11323 NXP Semiconductors Chapter 26: Digital Microphone Interface (DMIC) This data batching works without contribution of the core. When reaching the defined chunk buffer size, the DMA issues an interrupt to the Arm core for further processing of the data.
Page 197 UM11323 NXP Semiconductors Chapter 26: Digital Microphone Interface (DMIC) This also enables the system to realize different strategies for dealing with a HWVAD event. A concrete analysis of the data could for example just be started when the HWVAD detected events over a longer time frame. This would avoid that the Arm core gets active on spurious noise.
Page 198 UM11323 Chapter 27: 12-bit ADC Controller (ADC) Rev. 1.1 — June 2020 User manual 27.1 How to read this chapter The ADC controller is available on all K32W061/41 devices. 27.2 Features • 12-bit successive approximation analog to digital converter. •...
Page 199 UM11323 NXP Semiconductors Chapter 27: 12-bit ADC Controller (ADC) – Use the ADC clock, determined by the SYSCON_ADCCLKSEL register and the SYSCON_ADCCLKDIV register. ADC clock should be at 4 MHz. Some clock sources are independent of the system clock, and may require extra time to synchronize ADC trigger inputs.
Page 200 UM11323 NXP Semiconductors Chapter 27: 12-bit ADC Controller (ADC) The ADC can also be triggered by two of the outputs of the PWM module, PWM_OUT8 and PWM_OUT9. See Chapter 18 “Pulse Width Modulation (PWM)” for details of how these PWM signals are generated. In addition to enabling the PWM function it must also be selected in the conversion sequence registers for each ADC conversion sequence defined.
Page 201 UM11323 NXP Semiconductors Chapter 27: 12-bit ADC Controller (ADC) 27.5 General description Sequence A Pin interrupt 0 Start Complete IRQ PWM_OUT8 conversion Conversion Data overrun IRQ PWM_OUT9 Trigger to NVIC ARM_TXEV Threshold threshold IRQ compare Analog-to- Channel Channel Digital select...
Page 202 UM11323 NXP Semiconductors Chapter 27: 12-bit ADC Controller (ADC) 27.6.2 Hardware-triggered conversion Software can select which hardware trigger will launch each conversion sequence and it can specify the active edge for the selected trigger independently for each conversion sequence. For each conversion sequence, if a designated trigger event occurs, one single cycle through that conversion sequence will be launched unless: •...
Page 203 UM11323 NXP Semiconductors Chapter 27: 12-bit ADC Controller (ADC) 27.6.4.1 Conversion-Complete or Sequence-Complete interrupts An interrupt/DMA trigger can either be asserted at the end of each ADC conversion performed as part of that sequence or when the entire sequence of conversions is completed.
Page 204 UM11323 NXP Semiconductors Chapter 27: 12-bit ADC Controller (ADC) Two clocking modes are available, synchronous mode and asynchronous mode. The synchronous clocking mode uses the system clock in conjunction with an internal programmable divider. The main advantage of this mode is determinism. The start of ADC sampling is always a fixed number of system clocks following any ADC trigger.
Page 205 UM11323 NXP Semiconductors Chapter 27: 12-bit ADC Controller (ADC) Table 60. ADC0 hardware trigger inputs Input # Source Description PINT0 Chapter 16 “Group GPIO Input Interrupt (GINT)” PWM_OUT8 Chapter 18 “Pulse Width Modulation (PWM)” PWM_OUT9 Chapter 18 “Pulse Width Modulation (PWM)”...
Page 206 UM11323 NXP Semiconductors Chapter 27: 12-bit ADC Controller (ADC) To perform a single ADC conversion for channel 1 using the analog signal on pin ADC1, follow these steps: 1. Enable the analog function on pin ADC1 via IOCON. 2. Configure the system clock to be 48 MHz and configure SYSCON_ADCCLKSEL[SEL] to 00b (XO32M), configure SYSCON_ADCCLKDIV[DIV] to 111b (8, to have 4 MHz).
Page 207 UM11323 NXP Semiconductors Chapter 27: 12-bit ADC Controller (ADC) 27.7.3 Perform a conversion in full speed The goal is to have a full speed conversion of 1 input of ADC in channel 0. 1. Enable analog function for ADC0 2. Configure the system clock for ADC, 4 MHz clock is required and enable axync_adc_clk 3.
Page 208 UM11323 Chapter 28: Temperature Sensor Rev. 1.1 — June 2020 User manual 28.1 How to read this chapter The temperature sensor is available on all K32W061/41 devices. 28.2 Features • Linear temperature sensor. • Sensor output internally connected to the ADC channel 7 for temperature monitoring 28.3 Basic configuration...
Page 209 UM11323 NXP Semiconductors Chapter 28: Temperature Sensor To perform a single ADC conversion for ADC0 channel 7 using the temperature sensor output: 1. Enable the temperature sensor output as input to ADC channel 7. 2. Configure the system clock and the ADC for operation.
Page 210 Chapter 29: Serial Wire Debug (SWD) Rev. 1.1 — June 2020 User manual 29.1 How to read this chapter Serial Wire Debug functionality is available on all K32W061/41 devices. 29.2 Features • Supports Arm Serial Wire Debug mode for the Cortex-M4.
Page 211 UM11323 NXP Semiconductors Chapter 29: Serial Wire Debug (SWD) 2. If the clock to the IOCON block is not already enabled, write 1 to SYSCON_AHBCLKCTRLSET0[IOCON_CLK_SET]. The clock must be enabled in order to access any IOCON registers. 3. Configure the IOCON function for the required GPIO which will be used; for instance configure PIO0_17 to be FUNC3 by writing FUNC=3 in the PIO[17] register.
Page 212 UM11323 NXP Semiconductors Chapter 29: Serial Wire Debug (SWD) Serial-Wire Debug connection SWJ-DP Cortex-M4 Note: for protection it is not possible to access the debug functionality in some modes Fig 84. Serial Wire Debug connections K32W061 All information provided in this document is subject to legal disclaimers.
Page 213 UM11323 Chapter 30: Flash Controller Rev. 1.1 — June 2020 User manual 30.1 Introduction This chapter describes the Flash Controller of the K32W061/41 device. 30.2 Features • 32-bit AHB interface, to access the memory • 32-bit APB registers interface (same clock domain as AHB) •...
Page 214 Chapter 31: SRAM Controller Rev. 1.1 — June 2020 User manual 31.1 How to read this chapter Two SRAM controllers are available on all K32W061/41 devices. 31.2 Features The two controllers are connected as the following: Fig 85. SRAM controller connection The SRAM controllers have the following features: •...
Page 215 SRAM10 (16KB) • SRAM11 (16KB) Figure 1 “Main memory map” shows the K32W061/41 system memory map. 31.5 Power description 31.5.1 K32W061/41 IC power domains The two SRAM controllers are on MCU power domain (PD_MCU) while memories are on different power domains PD_MEMx (see Section 31.5.2 “Memories power domains”...
Page 216 UM11323 NXP Semiconductors Chapter 31: SRAM Controller • PD_MEM6 for SRAM6 • PD_MEM7 for SRAM7 • PD_MEM8 for SRAM8 • PD_MEM9 for SRAM9 • PD_MEM10 for SRAM10 • PD_MEM11 for SRAM11 In ACTIVE mode, SRAM memories are powered by LDO_CORE. If retention is needed (optional mode), SRAM memories are powered by LDO_MEM in power down mode.
Page 217 Chapter 32: ROM Controller Rev. 1.1 — June 2020 User manual 32.1 How to read this chapter The ROM controller is available on all K32W061/41 devices. 32.2 Features The ROM controller is connected as the following figure Fig 86. ROM controller connection The ROM controller has the following features: •...
Page 218 UM11323 NXP Semiconductors Chapter 32: ROM Controller Table 63. ROM setting Instance Type Slave Description Aperture Start Address End Address Power Name Port/Slave Size Domain Number Slave Code 128 KB 0x0300_0000 0x0401_FFFF K32W061 All information provided in this document is subject to legal disclaimers.
Page 219 • Finally, the last 64 bits contain the length of the whole message, in bits, formatted as a word. K32W061 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2020. All rights reserved. User manual Rev.
Page 220 UM11323 NXP Semiconductors Chapter 33: Hash-Crypt Peripheral for SHA1, SHA2 (HASH) The data is fed by words from the processor, DMA, or hosted access; the words are converted from little-endian (Arm standard) to big-endian (SHA standard) by the block. So, no extra work is needed.
Page 221 UM11323 NXP Semiconductors Chapter 33: Hash-Crypt Peripheral for SHA1, SHA2 (HASH) – The hashing then runs for 64 or 80 cycles. – The DMA is then requested to load another 16. When the DMA is done, it interrupts the processor.
Page 222 UM11323 NXP Semiconductors Chapter 33: Hash-Crypt Peripheral for SHA1, SHA2 (HASH) – An interrupt is used to notify the processor when the DMA completes. That ISR can enable the DIGEST interrupt (as well as ERROR) to process the results. Or, it can configure the DMA for more data if needed.
Page 223 UM11323 NXP Semiconductors Chapter 33: Hash-Crypt Peripheral for SHA1, SHA2 (HASH) src = (struct HASH_W * )memory_to_read_from; // use location in Flash or RAM dst = (struct HASH_W * )HASH0_INDATA; // indata and aliases dst[0] = src[0]; // 1st 8, usually using LDM/STM for best performance dst[0] = src[1];...
Page 224 “Supported QSPI devices”). • A driver library available from NXP Semiconductors to assist in using the SPIFI. • Four line cache to improve efficiency, when directly accessing data (memory mode) from external flash memory. Each cache line is 8 bytes.
Page 225 UM11323 NXP Semiconductors Chapter 34: SPI Flash Interface (SPIFI) Serial flash devices respond to commands sent by software or automatically sent by the SPIFI when software reads either of the two read-only serial flash regions in the memory map (see Table 66 “Supported QSPI...
Page 226 UM11323 NXP Semiconductors Chapter 34: SPI Flash Interface (SPIFI) Table 66: Supported QSPI devices Manufacturer Device name Elite (ESMT) F25L08P, F25L16P, F25L32P, F25L32Q EN25F10, EN25F20, EN25F40, EN25Q40, EN25F80, EN25Q80, EN25QH16, EN25Q32, EN25Q64, EN25Q128 Gigadevice GD25Q512, GD25Q10, GD25Q20, GD25Q40, GD25Q80, GD25Q16, GD25Q32, GD25Q64...
Page 227 UM11323 NXP Semiconductors Chapter 34: SPI Flash Interface (SPIFI) 34.8.2 SPIFI command register Writing to the Command Register can initiate the transmission of a new command. If the command requires additional data such as an address or intermediate data then this must be provided before the command is issued.
Page 228 UM11323 NXP Semiconductors Chapter 34: SPI Flash Interface (SPIFI) In polling mode (see the CMD[POLL]), one byte must be read from this register because the poll mechanism writes the matching byte. This register is not used for commands initiated by reading the flash address range in the memory map.
Page 229 UM11323 NXP Semiconductors Chapter 34: SPI Flash Interface (SPIFI) The SPI protocol avoids all issues of set-up and hold times between the clock and data lines by using half of the SCK period to transmit the data. For high clock speeds, it is necessary to sample read data using a feedback clock.
Page 230 UM11323 NXP Semiconductors Chapter 34: SPI Flash Interface (SPIFI) Fig 88. Read commands In quad mode, the IO3:0 lines are driven by the SPIFI in opcode, address, intermediate and output data fields, and driven by the flash memory in input data fields. In address fields the more significant bytes are sent first.
Page 231 UM11323 NXP Semiconductors Chapter 34: SPI Flash Interface (SPIFI) The SPIFI has a small cache for accesses to the serial flash region of the memory map. The cache is only used in Memory mode and can be disabled. Because the SPIFI is an AHB device, software or a DMA channel can read bytes, halfwords, or words from the flash region.
Page 232 UM11323 NXP Semiconductors Chapter 34: SPI Flash Interface (SPIFI) To use this mode, software should write the Command register to start the command and program a DMA channel as described above to transfer data between the Data register and RAM. The SPIFI asserts the DMA request when: •...
Page 233 Generally, it is not practical to use this method to create the random number. It will give True Random number performance, K32W061 All information provided in this document is subject to legal disclaimers.
Page 234 UM11323 NXP Semiconductors Chapter 35: True Random Number Generator (TRNG) but it will take too long. A software procedure using this hardware entropy accumulation register is presented below and gives a usable method for generating random numbers which have True Random number performance.
Page 235 UM11323 NXP Semiconductors Chapter 35: True Random Number Generator (TRNG) Checking initial entropy, for total failure or low quality: There is no hardware self-checking mechanism. Some software procedure can be implemented: • Software can use the same procedure described above to read initial number in order to ensure a minimum entropy accumulation after power-up •...
Page 236 The digital part of the Contact Interface is composed of the following blocks: • APB slave interface • Registers • Sequencer K32W061 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2020. All rights reserved. User manual Rev. 1.1 — June 2020 236 of 350...
Page 237 UM11323 NXP Semiconductors Chapter 36: ISO 7816 Smart Card Interface • Timers • ATR counter • ISO USART Fig 89. Block diagram of Contact Interface (Digital Part) The Contact Interface is a card interface for smart card reader. The Contact Interface supports both synchronous and asynchronous 5V, 3V and 1,8V smart cards.
Page 238 UM11323 NXP Semiconductors Chapter 36: ISO 7816 Smart Card Interface Table 67. Register accesses causing a hardfault Access Type APB interface response Write to a read-only register No effect. Register not updated Read from a write-only register Read 00000000h Write to an RFU address...
Page 239 UM11323 NXP Semiconductors Chapter 36: ISO 7816 Smart Card Interface 36.3.3 Sequencer The digital sequencer manages activation and deactivation sequences. To perform the sequences, the SSR[SEQ_EN] bit must be set. The sequencer is mainly composed of a FSM (finite state machine) four states: inactive_state, activation_state, active_state, deactivation_state.
Page 240 UM11323 NXP Semiconductors Chapter 36: ISO 7816 Smart Card Interface The sequencer controls when the I/O is enabled (enable_io), when the CLK starts (enable_clk) and RST is enabled (enable_rst). The time T below is about 24 s. In synchronous mode, after 24T/2, since enable_rst is at logic level one, RST is the copy of PCR[RSTIN] bit.
Page 241 UM11323 NXP Semiconductors Chapter 36: ISO 7816 Smart Card Interface Fig 92. Deactivation Sequence 36.3.3.1 Card 1 clock circuitry The digital card 1 clock circuitry generates the card 1 clock from the clk_ip clock. It manages card 1 clock dynamic frequency switches. The card 1 clock generation is composed of several stages.
Page 242 UM11323 NXP Semiconductors Chapter 36: ISO 7816 Smart Card Interface The frequency change is synchronous, which means that during transition, no pulse is shorter than 45% of the smallest period and that the first and last clock pulse around the change has the correct width.
Page 243 UM11323 NXP Semiconductors Chapter 36: ISO 7816 Smart Card Interface 3. If no start bit has been detected until 42100 (or the value written in MCRL[15:0] bits) CLK cycles, RST is set to logic level one. 4. If a start bit is detected within the first 370 (or 200 + the value written in ECR[ECR] bits) CLK cycles with RST at logic level one, the bit USR1[EARLY] is set to logic level one.
Page 244 UM11323 NXP Semiconductors Chapter 36: ISO 7816 Smart Card Interface Fig 94. Timer block diagram Remark: USART_START_N indicates a start bit has occurred. Remark: wr_toc indicates a write in TOC register has occurred. The three registers TOR1, TOR2 and TOR3 form a programmable 24-bit ETU counter, or two independent counters (16-bit and 8-bit), or three independent 8-bit counters.
Page 245 UM11323 NXP Semiconductors Chapter 36: ISO 7816 Smart Card Interface The TOC register is used for setting different configurations of the time-out counter: • If 16/24 and 8/16 bits are logic 0, then the counter is wired as a single 24-bit counter loaded with registers TOR3 (MSB byte), TOR2 and TOR1 (LSB byte).
Page 246 UM11323 NXP Semiconductors Chapter 36: ISO 7816 Smart Card Interface When counters 3 and 2 form a 16-bit counter, if counter 2 mode is triggered on start bit on I/O and counter 3 mode is software triggered, then the mode of this 16-bit counter is triggered on start bit on I/O.
Page 247 UM11323 NXP Semiconductors Chapter 36: ISO 7816 Smart Card Interface Fig 95. ISO USART block diagram The block Clock circuitry provides a signal which enables to count (ETU_cnt_en). It also embeds a counter (ETU_counter) used for reception and transmission according to the frequency of the card clock.
Page 248 UM11323 NXP Semiconductors Chapter 36: ISO 7816 Smart Card Interface – If the FIFO size pointer equals 32, no more character can be loaded into the FIFO. An Overrun interrupt will be generated by the ct_usr1_reg register to mean that at least one character will be lost.
Page 249 UM11323 NXP Semiconductors Chapter 36: ISO 7816 Smart Card Interface Fig 96. FIFO turnaround reception -> transmission Remark: When switching from/to reception to/from transmission mode, the FIFO is flushed (and the size pointer is reset). Any remaining bytes are lost.
Page 250 UM11323 NXP Semiconductors Chapter 36: ISO 7816 Smart Card Interface K32W061_dig clk_and_reset Smart card TDA80XX Analogue slot Apb bus ISO7816 Registers Fig 97. ISO7816 interface 36.4.1 Clock and Reset The functional clock of the ISO7816 block (clk_ip) is connected to system_ahb_clk[21] thus it is generated from the MAINCLK as all the AHB clocks.
Page 251 PIO0_2 in the fmux when mode is "110" • PIO0_16 in the fmux when mode is "010" 36.4.2 GPIO configuration 2 GPIOs configurations are available on K32W061/41 to use ISO7816 interface: • For IOCON_PIO[FUNC] = 010: – PIO0_16 = ISO7816_RST –...
Page 252 TEMPSENSORCTRL. 37.5 External NFC tag For the K32W061 devices there is an NFC tag within the package. The I C2 block is used to communicate with the tag. The power for the tag is controlled from an IO cell. Before the tag can be used, the IO cells and tag power need to be configured correctly.
Page 253 UM11323 NXP Semiconductors Chapter 37: Async System Configuration (ASYNC_SYSCON) 37.6 Frequency measurement The frequency measurement block can be used to measure the frequency of one clock using another clock of known frequency. The block has two clock inputs: reference clock and target clock. A scaler, SCALE, is SCALE programmed.
Page 254 UM11323 NXP Semiconductors Chapter 37: Async System Configuration (ASYNC_SYSCON) 0000 CLK_IN[PIO_19] XTAL 32MHz 0001 FRO 1MHz 0010 Target_clock 32 kHz[CLK_32KHz] 0011 To frequency measure ref_clock 0100 Divided Main Clock[SYSTEM AHBCLK] PIO[4] 0101 PIO[20] 0110 Device Pins PIO[16] 0111 PIO[15] 1000 Inmux.freqmeas_target...
Page 255 Rev. 1.1 — June 2020 User manual 38.1 How to read this chapter ISP functionality is supported by the boot code on all K32W061/41 devices. 38.2 Features All K32W061/41 devices include ROM-based services for programming and reading the flash memory in addition to other functions. In-System Programming works on an unprogrammed or previously programmed device using a USART interface.
Page 256 UM11323 NXP Semiconductors Chapter 38: In-System Programming (ISP) Fig 100. Standard packets format Each field is described individually in the following sections. Any value that spans more than one byte is usually sent big-endian: the most significant byte is transmitted first. Exceptions to this rule are noted in the descriptions.
Page 257 UM11323 NXP Semiconductors Chapter 38: In-System Programming (ISP) Table 75: Type field Value Command Request Response Unlock ISP 0x4E 0x4F Use Certificate 0x50 0x51 Start Encrypted Transfer 0x52 0x53 In each case, the Response value is the same as the Request value but with bit 0 inverted.
Page 258 UM11323 NXP Semiconductors Chapter 38: In-System Programming (ISP) Table 76: Status code Status Descriptions 0x00 Success 0xEF Memory invalid mode 0xF0 Memory bad state 0xF1 Memory too long 0xF2 Memory out of range 0xF3 Memory access invalid 0xF4 Memory not supported...
Page 259 UM11323 NXP Semiconductors Chapter 38: In-System Programming (ISP) 38.6.1.2 Execute This command executes (runs) code in flash or RAM. The response is sent before execution jumps to the provided address. The Request Payload contains the following fields: Table 77: Execute field descriptions...
Page 260 UM11323 NXP Semiconductors Chapter 38: In-System Programming (ISP) The Response Payload contains the following fields: Table 81: Get device info fields descriptions Field Offset Size Description Handle Handle to be used with subsequent access commands NOTE: Current implementation always returns 0, and only one memory type can be accessed at a time 38.6.1.6 Read memory...
Page 261 UM11323 NXP Semiconductors Chapter 38: In-System Programming (ISP) Table 85: Erase memory request fields descriptions Field Offset Size Description Handle Handle returned by open memory command (see Section 38.6.1.5) Mode Erase mode: always use 0 Address Address within memory to start erasing from...
Page 262 Access Access rights, as a bitmap of multiple options (see table of access bit values, below) Name ASCII name of memory block The following memory IDs are supported on the K32W061/41: Table 90: K32W061/41 supported memory ID Memory ID Name...
Page 263 UM11323 NXP Semiconductors Chapter 38: In-System Programming (ISP) Table 91: K32W061/41 available basic memory types Type ID Name FLASH EFUSE (OTP) The following access bit values are available: Table 92: K32W061/41 available access bit values Memory ID Name Read enabled...
Page 264 UM11323 NXP Semiconductors Chapter 38: In-System Programming (ISP) For security, the OTP and protected sector are locked during ISP. To erase these areas, a mass erase of all other data will be performed and the unlock key written to the protected sector update page.
Page 265 UM11323 NXP Semiconductors Chapter 38: In-System Programming (ISP) The encryption Key is encrypted with the device firmware update key using AESKW. This allows for a firmware image to be encrypted with a unique key which is then securely provided to the device. Each device may then have a unique update key without requiring individual device images.
Page 266 UM11323 NXP Semiconductors Chapter 38: In-System Programming (ISP) Open Memory ID 3 (Configuration) for Access TX 00 00 0A 40 03 01 F2 CF AF 52 RX 00 00 0A 41 00 00 AF 27 A6 30 Read Memory (8 bytes from offset 0x9FC70)
Page 267 UM11323 NXP Semiconductors Chapter 38: In-System Programming (ISP) 01 04 81 01 00 00 A3 01 00 00 A5 01 00 00 A7 01 ..25 4B 98 47 81 1E 48 42 04 F0 7F 04 48 41 96 19...
Page 268 UM11323 NXP Semiconductors Chapter 38: In-System Programming (ISP) Read Memory (0x200 bytes from offset 0x200) TX 00 00 12 46 00 00 00 02 00 00 00 02 00 00 9B 7E 1C 4F RX 00 02 09 47 00 40 2C 05 D1 21 4B 2B 40 1A 1F 53 42 53 41 00 E0 00 23 03 42 E6 D0 4F F0 80 43 D3 ..
Page 269 UM11323 NXP Semiconductors Chapter 38: In-System Programming (ISP) RX 00 00 09 15 00 FE 46 2A 86 38.8 Usage restrictions It is possible to restrict access to the ISP functionality, for instance in order to protect code in the flash.
Page 270 • Integrated GF128 hash engine for Galois Counter Mode (GCM) • Supported modes: ECB, CBC, CFB, OFB, CTR, GCM K32W061 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2020. All rights reserved. User manual Rev.
Page 271 UM11323 NXP Semiconductors Chapter 39: Advanced Encryption Standard (AES) 39.3 Function description The AES engine uses 128-bit, 192-bit or 256-bit key and processes blocks of 128 bits. Encrypting and decrypting data, storing and retrieving the key. An AES encryption/decryption engine. Encryption/decryption is selected through the CFG register.
Page 272 Chapter 39: Advanced Encryption Standard (AES) 39.4 Software interface The AES registers are accessible through an AHB slave port. This section gives a brief description of the AES registers, please refer to section of the K32W061/41 Registers document for more details. 39.4.1 AES Configuration register The Configuration register allows to select the features of the AES like: •...
Page 273 UM11323 NXP Semiconductors Chapter 39: Advanced Encryption Standard (AES) • Read the encrypted text from OUTTEXT0-OUTTEXT3 registers 39.5.2 Encryption with DMA This section describes an example of using the AES block with DMA; this mode allows to execute data encryption without using the CPU for better efficiency.
Page 274 Chapter 40: Infra-Red Modulator (CIC_IRB) Rev. 1.1 — June 2020 User manual 40.1 How to read this chapter One Infra-Red Modulator (IRB) is available on all K32W061/41 devices. 40.2 Features • Transmission of data over an InfraRed link to another system or device •...
Page 275 UM11323 NXP Semiconductors Chapter 40: Infra-Red Modulator (CIC_IRB) Table 100. Suggested IR Blaster pin setting for standard GPIO IO IOCON bit(s) Field Setting Note Slew1 With slew0: generally set to 0. Settings to 1,2 or 3 at high usary rates may improve performance...
Page 276 UM11323 NXP Semiconductors Chapter 40: Infra-Red Modulator (CIC_IRB) Prescaler CARRIER generator ENVELOPE generator OUTPUT LOGIC (and, or, nand, nor) Fig 104. IR blaster block diagram IR Blaster can be used in 2 modes according to the CONF[MODE]: • Normal mode:...
Page 277 UM11323 NXP Semiconductors Chapter 40: Infra-Red Modulator (CIC_IRB) Fig 105. Normal mode • Automatic restart In this mode, IR Blaster transmit all the data present in FIFO regardless of the FIFO_IN[ENV_LAST] field. It will stop only when FIFO becomes empty (this event generates FIFO_UFL_INT interrupt).
Page 278 UM11323 NXP Semiconductors Chapter 40: Infra-Red Modulator (CIC_IRB) 40.7 Programming examples Some programming example for RC5, RC6, RCMM and SIRCS are provided in this section of the document. In addition there is an example for RC5 within the SDK. The configuration assumes that the clock for the Infra-Red Modulator is 48 MHz.
Page 279 UM11323 NXP Semiconductors Chapter 40: Infra-Red Modulator (CIC_IRB) • CARRIER[CTU] = 444 = 0x1BC • CARRIER[CLOW] = 01b • CARRIER[CHIGH] = 00b • With this configuration, carrier period is (CARRIER[CTU] * (CARRIER[CLOW] + CARRIER[CHIGH] + 2)) / 48MHz = 27.75 s, and "ON" time is CARRIER[CTU] * (CARRIER[CHIGH] + 1) / 48MHz = 9.25 s.
Page 280 UM11323 NXP Semiconductors Chapter 40: Infra-Red Modulator (CIC_IRB) 40.7.3 RCMM The discussion below is based on the following data table giving the tolerances for RCMM protocol from a decoder point of view. Remark: 1T = 27,778 s Table 103. RCMM timings Carrier definition Tmin (s)
Page 281 LO frequency synthesizer functionality. The 32 MHz system clock, used within the analogue and digital is generated in this block. K32W061 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2020. All rights reserved.
Page 282 Radio Controller Fig 107. Radio system block diagram 41.2 Radio analog transceiver The K32W061/41 features a highly configurable radio transceiver which supports a wide range of wireless protocols, including Zigbee/Thread, Thread, Bluetooth Low Energy. K32W061 All information provided in this document is subject to legal disclaimers.
Page 283 UM11323 NXP Semiconductors Chapter 41: 2.4 GHz Wireless Transceiver 41.2.1 Radio architecture The main features of the K32W061/41 analog radio are: • Single ended shared RF pin for receive and transmit operations • Each power domain has its own independent LDO (supplied by the top VDD_radio pin), as shown by the different colors.
Page 284 UM11323 NXP Semiconductors Chapter 41: 2.4 GHz Wireless Transceiver Fig 109. RF matching circuit 41.2.3 Fractional-N frequency synthesizer A low phase noise, fully integrated fractional-N frequency synthesizer is used in receive mode to provide the LO frequency used by the down-conversion mixer. It is also used in transmit mode to generate the modulated RF carrier.
Page 285 UM11323 NXP Semiconductors Chapter 41: 2.4 GHz Wireless Transceiver RX antenna diversity is supportted in order to mitigate frequency-selective fading effect due to multi-path propagation and improve link budget. Antenna diversity is supported for specific PHY configurations in 2.4 GHz.
Page 286 UM11323 NXP Semiconductors Chapter 41: 2.4 GHz Wireless Transceiver • Radio controller switches on the radio using the necessary sequences and timing control • Radio controller indicates to data path that transmit is ready • MAC/Link layer starts sending data at the required point •...
Page 287 UM11323 NXP Semiconductors Chapter 41: 2.4 GHz Wireless Transceiver The Bluetooth Low Energy applications can also use the wake-up timers if required. These could be used when no Bluetooth Low Energy connections are active; but they are not accurate enough to support Bluetooth Low Energy operation when a connection is active.
Page 288 UM11323 NXP Semiconductors Chapter 41: 2.4 GHz Wireless Transceiver • The PA is controlled to ramp the output power-up just before packet start, to avoid noise generation at the antenna. • Data from the baseband/modem is transmitted by modulating the PLL frequency •...
Page 289 UM11323 NXP Semiconductors Chapter 41: 2.4 GHz Wireless Transceiver • Calibration control; some radio blocks need to be configured in certain modes to support the calibration mechanisms. Therefore, these radio control settings need to be linked to calibration state machine settings. This is also covered in the TMU section.
Page 290 UM11323 NXP Semiconductors Chapter 41: 2.4 GHz Wireless Transceiver Fig 110. Radio interface control configuration K32W061 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2020. All rights reserved. User manual Rev. 1.1 — June 2020...
Page 291 UM11323 NXP Semiconductors Chapter 41: 2.4 GHz Wireless Transceiver 41.4.2 Timing Management Unit (TMU) The timing management unit combines the global TMU and some block level TMUs. The global TMU controls the radio groups, see Section 41.4.3 “Radio group controls”, and also triggers the other TMUs.
Page 292 UM11323 NXP Semiconductors Chapter 41: 2.4 GHz Wireless Transceiver Fig 112. Receive sequence of group enables Fig 113. Transmit sequence of group enables The central FSM of the TMU (Global TMU) decodes and executes the activation triggers received through LL/MAC control output or through register access.
Page 293 UM11323 NXP Semiconductors Chapter 41: 2.4 GHz Wireless Transceiver Upon reception of one of the listed triggers, the central TMU activates/deactivates one of the other TMU cores depending on the applied operation mode together with this trigger: • pre_start: This activation trigger is used to start/configure the analog front-end, run calibration loops, etc •...
Page 294 UM11323 NXP Semiconductors Chapter 41: 2.4 GHz Wireless Transceiver 41.4.5 RX Datapath The RX data-path is shown in the next diagram. sampling rates Res_mode Bluetooth LE 1: 8 Msps Bluetooth LE 2: 16Msps Zigbee/Thread: 16Msps 16 bit cnf reg Bluetooth LE2/Zigbee/Thread...
Page 295 UM11323 NXP Semiconductors Chapter 41: 2.4 GHz Wireless Transceiver • Spectral inversion: if required, I and Q channels can be swapped • AGC: receive chain gain must be controlled, especially at the start of reception to set a good signal to noise level, with headroom for interferer so that channel saturation does not occur.
Page 296 UM11323 NXP Semiconductors Chapter 41: 2.4 GHz Wireless Transceiver LNA gain for Transformer Attenuator gain LNA/mixer/IF amplifier AAF gain clip detector 1 Analog part gain 8.3 dB 0, -12, -18, -24, -36 dB gain 15.1, 27.1, 36.6 dB 0, 3, 6, 9, 12, 15, 18 dB output 12.6 dB...
Page 297 UM11323 NXP Semiconductors Chapter 41: 2.4 GHz Wireless Transceiver clipdet_en Power_down Power_down Comp_out Comp_out clipdet_out clip_amp_set<2:0> clipdet_rst Fig 117. Clip detector 1 41.5.3.2 Clip detector 2 The clip detector 2 senses the signal power at the output of the IF amplifier.
Page 298 UM11323 NXP Semiconductors Chapter 41: 2.4 GHz Wireless Transceiver clipdet_en Power_down Comp_out Comp_out clipdet_out clip_amp_set<2:0> clipdet_rst Fig 118. Clip detector 2 41.5.3.3 Clip detector 3 (post ADC) This detector indicates that clipping occurs if the signal at the ADC output is reaching the ADC full scale e.g.
Page 299 UM11323 NXP Semiconductors Chapter 41: 2.4 GHz Wireless Transceiver Thresholds used for calculating the gain reduction are: rx_datapath.clip_det_3_thr_1 and rx_datapath.clip_det_3_thr_2 Following a gain adjustment of the AAF, no detection is performed in clip detector 3 during: rx_datapath.clip_det_3_timeout 41.6 IEEE 802.15.4 Modem The modem performs all the necessary modulation and spreading functions required for digital transmission and reception of data at 250 kbits/s in the 2.4 GHz radio frequency...
Page 300 UM11323 NXP Semiconductors Chapter 41: 2.4 GHz Wireless Transceiver aaa-018590 Decimal code -105 Input power (dBm) Fig 120. Energy detect (ED) value versus input power level Other features supported by the modem are: • Generation of continuous wave (CW) and modulated carried test patterns for radio testing •...
Page 301 UM11323 NXP Semiconductors Chapter 41: 2.4 GHz Wireless Transceiver 10bit input I and Q data from common front end X-multiply De-rotator demod Clock 16Mhz Data to narrow band Symbol Out RSSI calculation Symbol Detector Sync RSSI RSSI / Energy New/ Legacy...
Page 302 UM11323 NXP Semiconductors Chapter 41: 2.4 GHz Wireless Transceiver protocol software layer performs the higher-layer aspects of the protocol, sending management and data messages between End Device and Coordinator nodes, using the services provided by the baseband processor. The MAC block diagram is shown below:...
Page 303 Part of the protocol allows for transmitted frames to be acknowledged by the destination sending an acknowledge packet within a very short window after the transmitted frame has been received. The K32W061 baseband processor can automatically construct and send the acknowledgment packet without processor intervention and hence avoid the protocol software being involved in time-critical processing within the acknowledge sequence.
Page 304 UM11323 NXP Semiconductors Chapter 41: 2.4 GHz Wireless Transceiver 41.7.6 System integration 41.7.6.1 Power domain Zigbee/Thread parts are localized in power domain MCU. When this power domain is switched off, which happens in power down mode for example, all internal settings are lost;...
Page 305 UM11323 NXP Semiconductors Chapter 41: 2.4 GHz Wireless Transceiver Bluetooth Low Energy protocol is controlled by the Link Layer (LL). It is responsible for advertising, scanning, creating and maintaining connections. Bluetooth Low Energy demodulator extracts from the intermediate frequency (IF) signal the bit stream carried by the GFSK modulation.
Page 306 UM11323 NXP Semiconductors Chapter 41: 2.4 GHz Wireless Transceiver • Resampler/Timing Error Detector (TED) • Reduced-State Viterbi Equalizer (RSVE) • Top-level state machine to control the demodulator operation during the packet 41.8.1.3 Link layer Link layer submodules control the Bluetooth Low Energy operation and handle the data stream to/from memory, including: •...
Page 307 UM11323 NXP Semiconductors Chapter 41: 2.4 GHz Wireless Transceiver EXCHANGE TABLE CONTROL STRUCTURE Control Structure PTR TX DESCRIPTOR TX DESCRIPTOR TX descriptor PTR Control Structure PTR TX descriptor PTR TX descriptor PTR Control Structure PTR TX data PTR TX data PTR...
Page 308 UM11323 NXP Semiconductors Chapter 41: 2.4 GHz Wireless Transceiver • Access is very slow, instead direct access to the SRAM should be used • There is possibility of a timeout depending upon other activities within the link layer and also any direct RAM accesses occurring. The timeout can occur after 64 cycles if a normal response has not occurred.
Page 309 UM11323 NXP Semiconductors Chapter 41: 2.4 GHz Wireless Transceiver • Center Frequency Offset (CFO) correction, based on offset estimation from the frequency domain processor • LUT-based design Fig 128. Example Signal before and after de-rotator, IF = 1 MHz, CFO = -200 kHz K32W061 All information provided in this document is subject to legal disclaimers.
Page 310 UM11323 NXP Semiconductors Chapter 41: 2.4 GHz Wireless Transceiver 41.8.2.1.3 Channel filter The channel filter is a low pass filter implemented by a 34 tap FIR. Different sets are available: • Wideband filter for initial burst/access address detection • Narrow band matched filter (2sets) 41.8.2.1.4 Resampler...
Page 311 UM11323 NXP Semiconductors Chapter 41: 2.4 GHz Wireless Transceiver Figure 130 “Example FM demodulator signals” shows: • The complex input signal, GFSK modulated • The output demodulated signal MODULATING FREQ OUT SCALER RE IN PHASE DEMOD IM IN Compute derivative to get modulating signal Fig 129.
Page 312 UM11323 NXP Semiconductors Chapter 41: 2.4 GHz Wireless Transceiver SYNC MODULE ESTIMATION TO RX FRONT END RESAMPLER PH SYMBOL TIMING RESAMPLER PHASE TO RX FRONT END SYNC FRAME METRIC SYNC INTEGRATE FREQUENCY DATA HARD DECISION DUMP FROM FM RX DATA FROM...
Page 313 UM11323 NXP Semiconductors Chapter 41: 2.4 GHz Wireless Transceiver 41.8.2.3.1 Burst detection and synchronization RSSI RSSI ESTIMATION TIMING Timing Triggers estimation DEMODULATOR XCORR output Fig 132. Burst detection and synchronisation General description of the algorithm: • A simplified cross correlation coupled with a FD RSSI based algorithm •...
Page 314 UM11323 NXP Semiconductors Chapter 41: 2.4 GHz Wireless Transceiver LATE SYMBOL EARLY SYMBOL CORRECT SYMBOL SAMPLING POINT SAMPLING POINT SAMPLING POINT nT- T/2 nT- T/2 nT- T/2 (n-1)T (n-1)T (n-1)T Fig 133. Gardner timing error computation The Gardner timing recovery algorithm requires two samples per symbol and knowledge...
Page 315 UM11323 NXP Semiconductors Chapter 41: 2.4 GHz Wireless Transceiver • whitened matched filter (see Section 41.8.2.1.6) is then used to generate min-phase channel impulse response. Reduced State Viterbi Equalizer (RSVE) is used to undo channel memory caused by partial response signaling of continuous phase signal and RX filtering.
Page 316 UM11323 NXP Semiconductors Chapter 41: 2.4 GHz Wireless Transceiver – Decoded data are sent to the link layer. Note that only frame payload and CRC bits are sent to the link layer (see Figure 135 “Demodulator operation”). Received signal IF domain...
Page 317 UM11323 NXP Semiconductors Chapter 41: 2.4 GHz Wireless Transceiver 41.8.3 Bluetooth Low Energy link layer TIMING REGISTERS GENERATORS INTERFACE RADIO FREQUENCY INTERRUPT MEMORY CONTROLLER SELECTION GENERATOR CONTROLLER EXCHANGE MEMORY CORE LEVEL Bluetooth LE CORE CONTROLLER BIT STREAM PACKET EVENT WHITE LIST...
Page 318 UM11323 NXP Semiconductors Chapter 41: 2.4 GHz Wireless Transceiver Input binary signal from demodulator PAYLOAD (variable length) (24 bits) White list engine activity WHITE LIST PARSING Fig 138. White list parsing White list addresses are 48 bits wide. They are read 16 bits at a time. It takes therefore 3 accesses to the exchange memory to read a full 48-bits address (see Figure 139 “White list engine state...
Page 319 UM11323 NXP Semiconductors Chapter 41: 2.4 GHz Wireless Transceiver IDLE Start and nb device not null READ 1 Check KO and nb device not null Read done CHECK 1 Check KO and nb device is null Address bits [15:0] matches...
Page 320 UM11323 NXP Semiconductors Chapter 41: 2.4 GHz Wireless Transceiver The device does not support device security, this is where some communication would be secure and some communication would be unsecure. 41.8.3.4 2 Mb/s mode The Bluetooth Low Energy subsystem operates at 1 Mb/s or 2 Mb/s data rate. The transmit and receive data rates are configured separately by using bits in the control structure.
Page 321 UM11323 NXP Semiconductors Chapter 41: 2.4 GHz Wireless Transceiver Interframe Spacing 150us RX Packet TX Packet TX_DELAY Delay from the end of the RX packet entering the TX_DELAY: Delay within radio before demod to when the last data bit is output to the...
Page 322 UM11323 NXP Semiconductors Chapter 41: 2.4 GHz Wireless Transceiver TX_DELAY: TX signal in radio has some delay within radio Interframe gap 150us TX Packet RX Packet Data in TX Packet RX Packet modem Link layer o/p Ble_tx_en Radio power up...
Page 323 UM11323 NXP Semiconductors Chapter 41: 2.4 GHz Wireless Transceiver 41.9 Calibrations 41.9.1 Introduction Various aspects of the radio need to be calibrated to take account of process variations and in some cases temperature variation. The radio software driver manages the calibration of the radio and the re-use of retained values as part of the radio initialization functions.
Page 324 UM11323 NXP Semiconductors Chapter 41: 2.4 GHz Wireless Transceiver The radio driver can manage recalibration if current temperature deviates too much from last calibration temperature. It needs actions from the application and from the MAC. For that, the application should regularly provide current temperature to the radio driver using vRadio_Temp_Update(int16_t s16Temp) API function where s16Temp is the current temperature in signed 12-bit 11.1 format (i.e.
Page 325 UM11323 NXP Semiconductors Chapter 41: 2.4 GHz Wireless Transceiver Current temperature (T ) is updated each time vRadio_Temp_Update() API is called. It is compared to the temperature of the last calibration (T ), and if the absolute difference between these two temperatures is greater than a threshold (default threshold value is 40°C), a calibration request flag is raised and written to the "always on"...
Page 326 For Bluetooth Low Energy, antenna diversity is purely managed by SW; the setting of a control bit selects the antenna to use. The K32W061/41 provides an output (ADO) on DIO7, DIO9 or DIO19 and optionally its complement (ADE) on DIO6, that can be used to control an antenna switch; this enables antenna diversity to be implemented easily (see the following two figures).
Page 327 UM11323 NXP Semiconductors Chapter 41: 2.4 GHz Wireless Transceiver antenna A antenna B SELA ADO (DIO7,DIO9, or DIO19) SELB RF switch: single-pole, double-throw (SPDT) ADE (DIO6) device RF port Fig 143. Simple antenna diversity implementation using external RF switch TX active...
Page 328 UM11323 NXP Semiconductors Chapter 41: 2.4 GHz Wireless Transceiver 41.12 Radio controller APIs To simplify use of the radio, a software radio controller library is provided, this should be used to control the radio. The main initialization function, vRadio_RadioInit controls the 32M XTAL, radio settings, managing calibrations.
Page 329 UM11323 NXP Semiconductors Chapter 41: 2.4 GHz Wireless Transceiver The results of the calibration are used when a transmit or receive operation occurs. For instance, in receive, the DC offset module uses the calibration results to cancel the expected offsets. Whenever a radio enters transmit or receive, the operating point for the PLL is managed by the hardware by interpolating between the calibration results for the PLL.
Page 330 Rev. 1.1 — June 2020 User manual 42.1 How to read this chapter This chapter presents the device features where an internal NTAG device is fitted. The K32W061 has an internal NTAG device. 42.2 Features • NTAG I C Plus device NT3H2211 is fitted •...
Page 331 UM11323 NXP Semiconductors Chapter 42: NFC Tag (NTAG) 42.5 General description The architecture of the core die and NTAG within the device is shown in Figure 145. For functional details of the NT3H2211 NTAG I C Plus device, see the NXP NT3H2111/NT3H2211 Data Sheet.
Page 332 UM11323 NXP Semiconductors Chapter 42: NFC Tag (NTAG) Once the NTAG is powered, it is necessary to configure the IO cells associated with the NTAG/I C interface see Section 42.6.2. 42.6.2 Configuring the I C Interface There are dedicated IO cells for connecting to the embedded NTAG device. These are configured in the NFCTAGPADSCTRL register as shown in the following table.
Page 333 UM11323 NXP Semiconductors Chapter 42: NFC Tag (NTAG) Before entering either of these power-down states, it is necessary to enable the event to trigger a wake-up event. The wakeup event will be on either the rising edge or falling edge of the FD signal.
Page 334 Chapter • Reset of the Cortex-M4 resets the CPU register bank. • Memory features: The memory map for K32W061/41 devices is shown in Section 2.1.2. In addition, there are debug and trace options, see Chapter K32W061 All information provided in this document is subject to legal disclaimers.
Page 335 UM11323 NXP Semiconductors Chapter 44: Supplementary information UM11323 Chapter 44: Supplementary information Rev. 1.1 — June 2020 User manual 44.1 Abbreviations Table 109. Abbreviations Acronym Description Analog-to-Digital Converter Advanced High-performance Bus AMBA Advanced Microcontroller Bus Architecture Advanced Peripheral Bus Application Programming Interface...
Page 336 UM11323 NXP Semiconductors Chapter 44: Supplementary information Table 109. Abbreviations …continued Acronym Description SRAM Static Random Access Memory Serial-Wire Debug Test Access Port USART Universal Synchronous/Asynchronous Receiver/Transmitter 44.2 References Cortex-M4 TRM — ARM Cortex-M4 Processor Technical Reference Manual UM10204 — I C-bus specification and user manual NIST/FIPS spec —...
Page 337 Table 40: Suggested USART pin setting for standard GPIO Table 90: K32W061/41 supported memory ID..262 IO ........149 Table 91: K32W061/41 available basic memory types .
Page 338 UM11323 NXP Semiconductors Chapter 44: Supplementary information Table 95: Response possible status code ...263 Table 96: Request payload fields descriptions ..264 Table 97: Request payload fields descriptions ..264 Table 98: Encryption Mode.
Page 339 UM11323 NXP Semiconductors Chapter 44: Supplementary information 44.4 Figures Fig 1. Chip block diagram ......6 interrupt and stop on match are enabled ..130 Fig 2.
Page 340 UM11323 NXP Semiconductors Chapter 44: Supplementary information Fig 94. Timer block diagram .....244 Fig 95. ISO USART block diagram ....247 Fig 96.
Page 341 UM11323 NXP Semiconductors Chapter 44: Supplementary information 44.5 Contents Chapter 1: Introductory Information Introduction ......3 Block diagram .
Page 342 UM11323 NXP Semiconductors Chapter 44: Supplementary information Chapter 7: Reset, Boot and Wakeup Introduction ......55 7.2.3.3...
Page 343 UM11323 NXP Semiconductors Chapter 44: Supplementary information Chapter 14: General Purpose I/O (GPIO) 14.1 How to read this chapter ....91 14.5.1 Reading pin state ..... . 91 14.5.2...
Page 344 UM11323 NXP Semiconductors Chapter 44: Supplementary information 18.6.1 Prescaler ......123 18.6.5 Common PWM mode....124 18.6.2...
Page 345 UM11323 NXP Semiconductors Chapter 44: Supplementary information Chapter 24: Serial Peripheral Interfaces (SPI) 24.1 How to read this chapter ....157 24.6.3 Frame delays ......163 24.6.3.1...
Page 346 Power description ..... 215 31.5.1 K32W061/41 IC power domains ..215 31.3 Basic configuration .
Page 347 UM11323 NXP Semiconductors Chapter 44: Supplementary information 34.8.1 SPIFI control register ....226 34.8.8 SPIFI status register ....228 34.8.2...
Page 348 UM11323 NXP Semiconductors Chapter 44: Supplementary information 39.4.1 AES Configuration register ... . . 272 39.5.1 Encryption without DMA ....272 39.4.2...
Page 349 UM11323 NXP Semiconductors Chapter 44: Supplementary information 41.13 PHY Controller ......328 Chapter 42: NFC Tag (NTAG) 42.1...
Page 350 How to Reach Us: Information in this document is provided solely to enable system and software implementers to use NXP products. There are no express or implied copyright licenses granted hereunder to design or Home Page: fabricate any integrated circuits based on the information in this document. NXP reserves the right to nxp.com make changes without further notice to any products herein.
Page 351 NXP Semiconductors Document identifier: UM11323 Reference Manual Rev. 1.1, 06/2020 K32W061/K32W041 Register Manual General Business Information...
Page 352 Chapter 11 Windowed Watchdog Timer (WWDT)......... 306 11.1 WWDT register descriptions..........................306 Chapter 12 Real-Time Clock (RTC)..............313 12.1 RTC register descriptions............................313 Chapter 13 Universal Synchronous/Asynchronous Receiver/Transmitter (USART)......................318 13.1 USART register descriptions..........................318 K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 General Business Information NXP Semiconductors...
Page 353 Chapter 24 Advanced Encryption Standard (AES)........554 24.1 AES register descriptions............................554 Chapter 25 Infra-Red Modulator (CIC_IRB)........... 567 25.1 CIC_IRB register descriptions..........................567 Chapter 26 Bluetooth Low Energy (BLE)............579 26.1 BLE register descriptions............................579 K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 NXP Semiconductors General Business Information...
Page 354 GPIO Other Reset Status Capture Register (PIORESCAP) description Low Power Mode Module Power Control Register (PDSLEEPCFG) description Analog Blocks Power Control Register (PDRUNCFG) description Table continues on the next page... K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 General Business Information NXP Semiconductors...
Page 355 Reserved. User software should write zeroes to reserved bits. The value read from a reserved bit is not defined. Software Reset Enable SWRRESETEN If set, it enables the software reset to affect the system. ABLE Table continues on the next page... K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 NXP Semiconductors General Business Information...
Page 356 Power Mode Control 00b - Active. LPMODE 01b - Deep Sleep. 10b - Power-Down. 11b - Deep Power-Down. 1.1.3 Flash Core LDO Control Register (LDOFLASHCORE) Offset Register Offset LDOFLASHCORE K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 General Business Information NXP Semiconductors...
Page 357 This reigster configures the brown out detector. The contents of this register are controlled by the boot code and the low-power API software and it is reset by POR, RSTN, WWDT. K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 NXP Semiconductors General Business Information...
Page 358 This reigster enables output of the high speed FRO. It is controlled by the boot code and the Low-power API software and it is reset by POR, RSTN, WWDT. K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 General Business Information NXP Semiconductors...
Page 359 1xxxx: Not applicable 19-0 RESERVED — User software should not modify the values in these fields. 1.1.6 1 MHz Free Running Oscillator Control Register (FRO1M) Offset Register Offset FRO1M K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 NXP Semiconductors General Business Information...
Page 360 Offset Register Offset ANAMUXCOMP Function This register configures the analog compator and the input selection to the comparator. It is reset by all reset sources, except Arm system reset. K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 General Business Information NXP Semiconductors...
Page 361 0b - No hysteresis. COMP_HYST 1b - Hysteris enabled. RESERVED — Reserved. User software should write zeroes to reserved bits. The value read from a reserved bit is not defined. K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 NXP Semiconductors General Business Information...
Page 362 Wakeup by PIOn 21-0 0b - Disable wakeup from power-down and deep power-down modes by PIOn. PIOn 1b - Enable wakeup from power-down and deep power-down modes by PIOn. K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 General Business Information NXP Semiconductors...
Page 363 High Speed FRO (FRO 192 MHz) Clock Valid Signal FRO192MCLKV The FRO192M clock generator also generates the FRO12M, FRO32M and FRO48M clock signals. These ALID sre valid when this flag is assertetd. K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 NXP Semiconductors General Business Information...
Page 364 Watchdog Timer Reset WDTRESET Read '1', the last chip reset was caused by the Watchdog Timer. Write '1' to clear this bit. Table continues on the next page... K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 General Business Information NXP Semiconductors...
Page 365 Its value is reset by all reset sources, except Arm system reset. Diagram Bits DATA31_0 Reset Bits DATA31_0 Reset K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 NXP Semiconductors General Business Information...
Page 366 RSTN. Diagram Bits DATA31_0 Reset Bits DATA31_0 Reset Fields Field Function 31-0 General Purpose always on Domain Data Storage DATA31_0 Only reinitialized on Power-On Reset and RSTN Pin reset. K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 General Business Information NXP Semiconductors...
Page 367 Capture of NTAG_FD Value at Power-on-reset and Pin Reset NTAG_FD Only valid on devices fitted with internal NFC Tag. Capture of PIO Values at Power-on-reset and Pin Reset 21-0 GPIO K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 NXP Semiconductors General Business Information...
Page 368 Reserved. User software should write zeroes to reserved bits. The value read from a reserved bit is not defined. Capture of NTAG_FD Value NTAG_FD Only valid on devices fitted with internal NFC Tag. Capture of GPIO Values 21-0 GPIO K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 General Business Information NXP Semiconductors...
Page 369 Enable MCU Power Domain State Retention EN_PDMCU_R This field enables MCU Power Domain state retention when entering in 'Powerdown' mode for modem ETENTION and radio cal values Table continues on the next page... K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 NXP Semiconductors General Business Information...
Page 370 0b - Bias is disabled in Power down and Deep Power down modes. 1b - Bias is enabled in Power down and Deep Power down modes. Table continues on the next page... K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 General Business Information NXP Semiconductors...
Page 371 Function 31-28 RESERVED — Reserved. User software should write zeroes to reserved bits. The value read from a reserved bit is not defined. Table continues on the next page... K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 NXP Semiconductors General Business Information...
Page 372 Power-Down mode or Deep Power-Down mode. Additionally, for devices which have the NTAG device fitted, it will identify if the field detect line caused the wake-up. It is reset by POR, RSTN, WWDT. K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 General Business Information...
Page 373 Only valid on devices fitted with internal NFC Tag. Wake-up Triggered by PIO n 21-0 GPIOn 1.1.18 Extension of CTRL Register (CTRLNORST) Offset Register Offset CTRLNORST Function This register will never be reset except by POR. K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 NXP Semiconductors General Business Information...
Page 374 3 bits for the different wake-up sources:generic async wake up event as selected by SLEEPCON/ STARTER0/1, IO wake-up event, RSTN pad event. If required, this field should only be managed by the Low-power driver software. K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 General Business Information NXP Semiconductors...
Page 375 204h AHB Clock control Register 1 (AHBCLKCTRL1) description 220h AHBCLKCTRL0 Bits Set Register (AHBCLKCTRLSET0) description 224h AHBCLKCTRL1 Bits Set Register (AHBCLKCTRLSET1) description Table continues on the next page... K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 NXP Semiconductors General Business Information...
Page 376 Digital microphone (DMIC) Subsystem Clock Source Selection Register (DMICCLKSEL) description 2F0h Wake-up Timer Clock Source Selection Register (WKTCLKSEL) description 300h SYSTICK Clock Divider Register (SYSTICKCLKDIV) description Table continues on the next page... K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 General Business Information NXP Semiconductors...
Page 377 Modem (Bluetooth) Status Register (MODEMSTATUS) description 5D4h XTAL 32 kHz Oscillator Capacitor Control Register (XTAL32KCAP) description 5D8h 32 MHz XTAL Control Register (XTAL32MCTRL) description Table continues on the next page... K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 NXP Semiconductors General Business Information...
Page 378 (WKT_LOAD_WKT0_LSB) A28h Wake-up Timer 0 Reload Value Most Significant Bits Register (WKT_ LOAD_WKT0_MSB) description A2Ch Wake-up Timer 1 Reload Value Register (WKT_LOAD_WKT1) description Table continues on the next page... K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 General Business Information NXP Semiconductors...
Page 379 GPIO_INT Synchonization First Stage Bypass Register (GPIOPSYN description FB0h Chip Revision ID and Number Register (DIEID) description FF0h Test Access Security Code Register (CODESECURITYPROT) description 2.1.2 Memory Remap Control Register (MEMORYREMAP) Offset Register Offset MEMORYREMAP K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 NXP Semiconductors General Business Information...
Page 380 Reserved. User software should write zeroes to reserved bits. The value read from a reserved bit is not defined. RESERVED — Reserved. User software should write zeroes to reserved bits. The value read from a reserved bit is not defined. Table continues on the next page... K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 General Business Information NXP Semiconductors...
Page 381 2.1.3 AHB Matrix Priority Control Register (AHBMATPRIO) Offset Register Offset AHBMATPRIO Diagram Bits AHBMATPRIO Reset Bits AHBMATPRIO Reset Fields Field Function 31-0 AHB Matrix Priority AHBMATPRIO The higher a setting, the higher the priority. K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 NXP Semiconductors General Business Information...
Page 382 10 ms period. SYSTICK frequency is a function of the mainclk and SYSTICKCLKDIV register. If the tick timer is configured to use the System clock directly, this value must reflect the 10 ms tick count for that clock. K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 General Business Information NXP Semiconductors...
Page 383 The number of the interrupt source within the interrupt array that acts as the Non-Maskable Interrupt (NMI) for the Cortex-M4, if enabled by NMIENM40. This can also cause the device to wakeup from sleep. 2.1.6 Asynchronous APB Control Register (ASYNCAPBCTRL) Offset Register Offset ASYNCAPBCTRL K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 NXP Semiconductors General Business Information...
Page 384 Enable Asynchronous APB Bridge and Subsystem ENABLE 2.1.7 Peripheral Reset Control Register 0 (PRESETCTRL0) Offset Register Offset PRESETCTRL0 100h Function The peripherals can be individually reset using the PRESETCTRL0 and PRESETCTRL1 registers. K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 General Business Information NXP Semiconductors...
Page 385 Real Time Clock (RTC) Reset Control 0b - Clear reset to the Real Time Clock module. RTC_RST 1b - Assert reset tothe Real Time Clock module. Table continues on the next page... K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 NXP Semiconductors General Business Information...
Page 386 1b - Assert reset to the BLE Low Power Control Module. Input Mux (INPUTMUX) Reset Control 0b - Clear reset to the INPUTMUX module. MUX_RST 1b - Assert reset to the INPUTMUX module. Table continues on the next page... K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 General Business Information NXP Semiconductors...
Page 387 Diagram Bits HASH DMIC_ RFP_ AES_ MODE BLE_R ZIGBE I2C2_ RNG_ PWM_ IR_RS SPI1_ Reserved _RST M_M... E_... Reset Bits SPI0_ I2C1_ I2C0_ USAR USAR Reserved T1_... T0_... Reset K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 NXP Semiconductors General Business Information...
Page 388 Random Number Generator (RNG) Reset Control 0b - Clear reset to the RNG module. RNG_RST 1b - Assert reset to the RNG module. Table continues on the next page... K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 General Business Information NXP Semiconductors...
Page 389 Reserved. User software should write zeroes to reserved bits. The value read from a reserved bit is not defined. 2.1.9 PRESETCTRL0 Bits Set Register (PRESETCTRLSET0) Offset Register Offset PRESETCTRLSET0 120h K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 NXP Semiconductors General Business Information...
Page 390 ANA_INT_CTR Writing one to this field sets the PRESETCTRL0[ANA_INT_CTRL_RST] bit L_RST_SET RTC_RST Set RTC_RST_SET Writing one to this field sets the PRESETCTRL0[RTC_RST] bit Table continues on the next page... K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 General Business Information NXP Semiconductors...
Page 391 MUX_RST Set MUX_RST_SE Writing one to this field sets the PRESETCTRL0[MUX_RST] bit SPIFI_RST Set SPIFI_RST_SE Writing one to this field sets the PRESETCTRL0[SPIFI_RST] bit Table continues on the next page... K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 NXP Semiconductors General Business Information...
Page 392 IR_RS SPI1_ Reserved _RS... RS... RST... RST... M_M... ST... E_... RS... RST... RST... T_... RS... Reset Bits SPI0_ I2C1_ I2C0_ USAR USAR Reserved RS... RS... RS... T1_... T0_... Reset K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 General Business Information NXP Semiconductors...
Page 393 PWM_RST Set PWM_RST_SE Writing one to this field sets the PRESETCTRL1[PWM_RST] bit. IR_RST Set IR_RST_SET Writing one to this field sets the PRESETCTRL1[IR_RST] bit. Table continues on the next page... K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 NXP Semiconductors General Business Information...
Page 394 2.1.11 PRESETCTRL0 Bits Clear Register (PRESETCTRLCLR0) Offset Register Offset PRESETCTRLCLR0 140h Function Clear bits in PRESETCTRL0. It is recommended that changes to PRESETCTRL0 registers be accomplished by using the related PRESETCTRLSET0 and PRESETCTRLCLR0 registers. K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 General Business Information NXP Semiconductors...
Page 395 RTC_RST RTC_RST_CLR Writing one to this field clears the PRESETCTRL0[RTC_RST] bit. WWDT_RST Clear WWDT_RST_C Writing one to this field clears the PRESETCTRL0[WWDT_RST] bit. Table continues on the next page... K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 NXP Semiconductors General Business Information...
Page 396 Writing one to this field clears the PRESETCTRL0[SPIFI_RST] bit. RESERVED — Reserved. User software should write zeroes to reserved bits. The value read from a reserved bit is not defined. Table continues on the next page... K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 General Business Information NXP Semiconductors...
Page 397 Function 31-28 RESERVED — Reserved. User software should write zeroes to reserved bits. The value read from a reserved bit is not defined. Table continues on the next page... K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 NXP Semiconductors General Business Information...
Page 398 IR_RST Clear IR_RST_CLR Writing one to this field clears the PRESETCTRL1[IR_RST] bit. SPI1_RST Clear SPI1_RST_CL Writing one to this field clears the PRESETCTRL1[SPI1_RST] bit. Table continues on the next page... K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 General Business Information NXP Semiconductors...
Page 399 2.1.13 AHB Clock Control Register 0 (AHBCLKCTRL0) Offset Register Offset AHBCLKCTRL0 200h Function Peripherals on the AHB bus have individual clocks which can be enabled and disabled individually in AHBCLKCTRL0 and AHBCLKCTRL1. K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 NXP Semiconductors General Business Information...
Page 400 Enable the clock for the Analog Interrupt Control module (for BOD and comparator status and interrupt control) ANA_INT_CTR 0b - Disable. 1b - Enable. Enable the clock for the RTC 0b - Disable. 1b - Enable. Table continues on the next page... K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 General Business Information NXP Semiconductors...
Page 401 Reserved. User software should write zeroes to reserved bits. The value read from a reserved bit is not defined. Enable the clock for the Input Mux 0b - Disable. 1b - Enable. Table continues on the next page... K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 NXP Semiconductors General Business Information...
Page 402 Reserved. User software should write zeroes to reserved bits. The value read from a reserved bit is not defined. 2.1.14 AHB Clock control Register 1 (AHBCLKCTRL1) Offset Register Offset AHBCLKCTRL1 204h K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 General Business Information NXP Semiconductors...
Page 403 Enable the clock for the AES 0b - Disable. 1b - Enable. Enable the clock for the Modem AHB Master Interface 0b - Disable. MODEM_MAST 1b - Enable. Table continues on the next page... K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 NXP Semiconductors General Business Information...
Page 404 Enable the clock for the I2C1 0b - Disable. I2C1 1b - Enable. Enable the clock for the I2C0 0b - Disable. I2C0 1b - Enable. Table continues on the next page... K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 General Business Information NXP Semiconductors...
Page 405 CLK... _CL... 16... CLK... CL... CL... Reset Bits Reserv GPIO_ IOCO Reserv MUX_ SPIFI_ Reserv Reserv SRAM SRAM Reserv Reserv Reserv Reserved CL... N_C... CLK... C... _CT... _CT... Reset K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 NXP Semiconductors General Business Information...
Page 406 GINT Set GINT_CLK_SE Writing one to this field sets the AHBCLKCTRL0[GINT] bit. PINT Set PINT_CLK_SE Writing one to this field sets the AHBCLKCTRL0[PINT] bit. Table continues on the next page... K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 General Business Information NXP Semiconductors...
Page 407 Writing one to this field sets the AHBCLKCTRL0[SRAM_CTRL1] bit. CLK_SET SRAM_CTRL0 Set SRAM_CTRL0_ Writing one to this field sets the AHBCLKCTRL0[SRAM_CTRL0] bit. CLK_SET Table continues on the next page... K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 NXP Semiconductors General Business Information...
Page 408 IR_CL SPI1_ Reserved _CL... CL... CLK... CLK... M_M... LK... E_... CL... CLK... CLK... K_... CL... Reset Bits SPI0_ I2C1_ I2C0_ USAR USAR Reserved CL... CL... CL... T1_... T0_... Reset K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 General Business Information NXP Semiconductors...
Page 409 PWM Set PWM_CLK_SE Writing one to this field sets the AHBCLKCTRL1[PWM] bit. IR Set IR_CLK_SET Writing one to this field sets the AHBCLKCTRL1[IR] bit. Table continues on the next page... K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 NXP Semiconductors General Business Information...
Page 410 The clocks for the AHB Peripherals can be enabled or disabled individually in AHBCLKCTRL0 and AHBCLKCTRL1. However, it can be more efficient to disable one or more clocks by just setting bits in the AHBCLKCTRLCLR0 and AHBCLKCTRLCLR1. K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 General Business Information...
Page 411 RTC Clear RTC_CLK_CLR Writing one to this field clears the AHBCLKCTRL0[RTC] bit. WWDT Clear WWDT_CLK_C Writing one to this field clears the AHBCLKCTRL0[WWDT] bit. Table continues on the next page... K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 NXP Semiconductors General Business Information...
Page 412 Writing one to this field clears the AHBCLKCTRL0[SPIFI] bit. RESERVED — Reserved. User software should write zeroes to reserved bits. The value read from a reserved bit is not defined. Table continues on the next page... K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 General Business Information NXP Semiconductors...
Page 413 The clocks for the AHB Peripherals can be enabled and disabled individually in AHBCLKCTRL0 and AHBCLKCTRL1. However, it can be more efficient to disable one or more clocks by just setting bits in the AHBCLKCTRLCLR0 and AHBCLKCTRLCLR1. K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 NXP Semiconductors General Business Information...
Page 414 BLE Clear BLE_CLK_CLR Writing one to this register clears the AHBCLKCTRL1[BLE] bit. ZIGBEE Clear ZIGBEE_CLK_ Writing one to this field clears the AHBCLKCTRL1[ZIGBEE] bit. Table continues on the next page... K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 General Business Information NXP Semiconductors...
Page 415 Writing one to this field clears the AHBCLKCTRL1[USART0] bit. 10-0 RESERVED — Reserved. User software should write zeroes to reserved bits. The value read from a reserved bit is not defined. K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 NXP Semiconductors General Business Information...
Page 416 100b - 48 MHz free running oscillator (FRO) 2.1.20 OSC32KCLK and OSC32MCLK Clock Sources Selection Register (OSC32CLKSEL) Offset Register Offset OSC32CLKSEL 284h Function Note: this register cannot be locked by CLOCKGENUPDATELOCKOUT register. K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 General Business Information NXP Semiconductors...
Page 417 OSC32MCLK Clock Source Selection 0b - 32 MHz free running oscillator (FRO) SEL32MHZ 1b - 32 MHz crystal oscillator 2.1.21 CLKOUT Clock Source Selection Register (CLKOUTSEL) Offset Register Offset CLKOUTSEL 288h K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 NXP Semiconductors General Business Information...
Page 418 101b - 48 MHz free running oscillator (FRO) 110b - 1 MHz free running oscillator (FRO) 111b - No clock 2.1.22 SPIFI Clock Source Selection Register (SPIFICLKSEL) Offset Register Offset SPIFICLKSEL 2A0h K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 General Business Information NXP Semiconductors...
Page 419 011b - Reserved 100b - No clock 101b - No clock 110b - No clock 111b - No clock 2.1.23 ADC Clock Source Selection Register (ADCCLKSEL) Offset Register Offset ADCCLKSEL 2A4h K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 NXP Semiconductors General Business Information...
Page 420 00b - 32 MHz crystal oscillator (XTAL) 01b - FRO 12 MHz 10b - No clock 11b - No clock 2.1.24 USART0 and USART1 Clock Source Selection Register (USARTCLKSEL) Offset Register Offset USARTCLKSEL 2B0h K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 General Business Information NXP Semiconductors...
Page 421 01b - 48 MHz free running oscillator (FRO) 10b - Fractional Rate Generator clock (see FRGCLKSEL) 11b - No clock 2.1.25 I2C0, I2C1 and I2C2 Clock Source Selection Register (I2CC LKSEL) Offset Register Offset I2CCLKSEL 2B4h K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 NXP Semiconductors General Business Information...
Page 422 01b - 48 MHz free running oscillator (FRO) 10b - No clock 11b - No clock 2.1.26 SPI0 and SPI1 Clock Source Selection Register (SPICLKSE Offset Register Offset SPICLKSEL 2B8h K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 General Business Information NXP Semiconductors...
Page 423 01b - 48 MHz free running oscillator (FRO) 10b - No clock 11b - No clock 2.1.27 Infra Red Clock Source Selection Register (IRCLKSEL) Offset Register Offset IRCLKSEL 2BCh Diagram Bits Reserved Reset Bits Reserved Reset K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 NXP Semiconductors General Business Information...
Page 424 Function 31-2 RESERVED — Reserved. User software should write zeroes to reserved bits. The value read from a reserved bit is not defined. Table continues on the next page... K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 General Business Information NXP Semiconductors...
Page 425 00b - Either 32 MHz FRO or 32 MHz XTAL (see OSC32CLKSEL) 01b - Either 32 kHz FRO or 32 kHz XTAL (see OSC32CLKSEL) 10b - 1 MHz FRO 11b - No Clock K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 NXP Semiconductors General Business Information...
Page 426 Zigbee/Thread Modem Clock Source Selection 0b - 32 MHz XTAL SEL_ZIGBEE 1b - No Clock 2.1.31 Fractional Rate Generator (FRG) Clock Source Selection Register (FRGCLKSEL) Offset Register Offset FRGCLKSEL 2E8h K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 General Business Information NXP Semiconductors...
Page 427 01b - Either 32 MHz FRO or 32 MHz XTAL (see OSC32CLKSEL) 10b - 48 MHz free running oscillator (FRO) 11b - No Clock 2.1.32 Digital microphone (DMIC) Subsystem Clock Source Selection Register (DMICCLKSEL) Offset Register Offset DMICCLKSEL 2ECh K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 NXP Semiconductors General Business Information...
Page 428 101b - 12 MHz free running oscillator (FRO) 110b - No clock 111b - No Clock 2.1.33 Wake-up Timer Clock Source Selection Register (WKTC LKSEL) Offset Register Offset WKTCLKSEL 2F0h K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 General Business Information NXP Semiconductors...
Page 429 10b - No clock 11b - No Clock 2.1.34 SYSTICK Clock Divider Register (SYSTICKCLKDIV) Offset Register Offset SYSTICKCLKDIV 300h Function The SYSTICK clock can drive the SYSTICK function within the processor. K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 NXP Semiconductors General Business Information...
Page 430 Divider ratio is (DIV+1). E.g. 0: Divide by 1 and 255: Divide by 256. 2.1.35 TRACE Clock Divider Register (TRACECLKDIV) Offset Register Offset TRACECLKDIV 304h Function This register is used for part of the Serial debugger (SWD) feature. K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 General Business Information NXP Semiconductors...
Page 431 Clock Divider Setting Divider ratio is (DIV+1). E.g. 0: Divide by 1 and 255: Divide by 256. 2.1.36 Watchdog Timer Clock Divider Register (WDTCLKDIV) Offset Register Offset WDTCLKDIV 36Ch K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 NXP Semiconductors General Business Information...
Page 432 Clock Divider Setting Divider ratio is (DIV+1). E.g. 0: Divide by 1 and 255: Divide by 256. 2.1.37 Infra Red Clock Divider Register (IRCLKDIV) Offset Register Offset IRCLKDIV 378h K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 General Business Information NXP Semiconductors...
Page 433 Clock Divider Setting Divider ratio is (DIV+1). E.g. 0: Divide by 1 and 15: Divide by 16. 2.1.38 System Clock Divider Register (AHBCLKDIV) Offset Register Offset AHBCLKDIV 380h K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 NXP Semiconductors General Business Information...
Page 434 Clock Divider Setting Divider ratio is (DIV+1). E.g. 0: Divide by 1 and 255: Divide by 256. 2.1.39 CLKOUT Clock Divider Register (CLKOUTDIV) Offset Register Offset CLKOUTDIV 384h K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 General Business Information NXP Semiconductors...
Page 435 Clock Divider Setting Divider ratio is (DIV+1). E.g. 0: Divide by 1 and 15: Divide by 16. 2.1.40 SPIFI Clock Divider Register (SPIFICLKDIV) Offset Register Offset SPIFICLKDIV 390h K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 NXP Semiconductors General Business Information...
Page 436 Clock Divider Setting Divider ratio is (DIV+1). E.g. 0: Divide by 1 and 3: Divide by 4. 2.1.41 ADC Clock Divider Register (ADCCLKDIV) Offset Register Offset ADCCLKDIV 394h K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 General Business Information NXP Semiconductors...
Page 437 Divider ratio is (DIV+1). E.g. 0: Divide by 1 and 7: Divide by 8. 2.1.42 Real Time Clock Divider (1 kHz clock generation) Register (RTCCLKDIV) Offset Register Offset RTCCLKDIV 398h K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 NXP Semiconductors General Business Information...
Page 438 Divider ratio is (DIV+1). E.g. 0: Divide by 1 and 31: Divide by 32. 2.1.43 Fractional Rate Generator Divider Register (FRGCTRL) Offset Register Offset FRGCTRL 3A0h Function The FRG is one of the USART clocking options. K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 General Business Information NXP Semiconductors...
Page 439 Denominator of the fractional divider is equal to the (DIV+1). Always set to 0xFF to use with the fractional baud rate generator : fout = fin / (1 + MULT/(DIV+1)) 2.1.44 DMIC Clock Divider Register (DMICCLKDIV) Offset Register Offset DMICCLKDIV 3A8h K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 NXP Semiconductors General Business Information...
Page 440 Divider ratio is (DIV+1). E.g. 0: Divide by 1 and 255: Divide by 256. 2.1.45 Real Time Clock Divider (1 Hz clock generation) Register (RTC1HZCLKDIV) Offset Register Offset RTC1HZCLKDIV 3ACh Function The divider is fixed to 32768 Hz K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 General Business Information NXP Semiconductors...
Page 441 Reserved. User software should write zeroes to reserved bits. The value read from a reserved bit is not defined. 2.1.46 Clock Configuration Registers Access Register (CLOC KGENUPDATELOCKOUT) Offset Register Offset CLOCKGENUPDATELO 3FCh CKOUT K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 NXP Semiconductors General Business Information...
Page 442 When set, it disables access to clock control registers (like xxxDIV, xxxSEL). It affects all clock control registers except OSC32CLKSEL. 2.1.47 Random Number Generator Clocks Control Register (RNGCLKCTRL) Offset Register Offset RNGCLKCTRL 59Ch Diagram Bits Reserved Reset Bits ENABL Reserved Reset K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 General Business Information NXP Semiconductors...
Page 443 Offset SRAMCTRL 5A0h Diagram Bits Reserved Reserved Reset Bits Reserved Reset Fields Field Function Reserved 31-19 — Reserved 18-2 — This field should only be modified by the APIs. K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 NXP Semiconductors General Business Information...
Page 444 BLE Phase Match 1 BLE_PHASE_M For normal BLE operation, set it to 0. BLE operation with this bit set to 1 is not supported. ATCH_1 Table continues on the next page... K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 General Business Information NXP Semiconductors...
Page 445 This is not needed for the standard method to enter power-down modes. 2.1.50 Modem (Bluetooth) Status Register (MODEMSTATUS) Offset Register Offset MODEMSTATUS 5D0h K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 NXP Semiconductors General Business Information...
Page 446 2.1.51 XTAL 32 kHz Oscillator Capacitor Control Register (XTAL 32KCAP) Offset Register Offset XTAL32KCAP 5D4h Function This register is used for selection of the internal capacitors to be used on each of the XTAL 32 kHz pins. K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 General Business Information NXP Semiconductors...
Page 447 Capacitance range is to apporximately 24 pF. 2.1.52 32 MHz XTAL Control Register (XTAL32MCTRL) Offset Register Offset XTAL32MCTRL 5D8h K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 NXP Semiconductors General Business Information...
Page 448 2.1.53 Start Logic 0 Wake-up Enable Register (STARTER0) Offset Register Offset STARTER0 680h Function Enable an interrupt for wake-up from deep-sleep mode. Some bits can also control wake-up from power-down mode K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 General Business Information NXP Semiconductors...
Page 449 1b - Wake-up enabled. Valid from Deep-Sleep and. PWM8 Interrupt Wake-up 0b - Wake-up disabled. PWM8 1b - Wake-up enabled. Valid from Deep-Sleep. Table continues on the next page... K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 NXP Semiconductors General Business Information...
Page 450 1b - Wake-up enabled. Valid from Deep-Sleep. SPI0 Interrupt Wake-up 0b - Wake-up disabled. SPI0 1b - Wake-up enabled. Valid from Deep-Sleep and Power-down. Table continues on the next page... K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 General Business Information NXP Semiconductors...
Page 451 1b - Wake-up enabled. Valid from Deep-Sleep. Pattern Interupt 1 (PINT1) Interrupt Wake-up 0b - Wake-up disabled. PINT1 1b - Wake-up enabled. Valid from Deep-Sleep. Table continues on the next page... K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 NXP Semiconductors General Business Information...
Page 452 SC... WAK... _UP... _UP... Reset Bits ANA_ ISO78 RFP_ RFP_T ZIGBE ZIGBE BLE_L BLE_D BLE_D BLE_D BLE_D HWVA ADC_ Reserv ADC_ DMIC COMP E_... E_... L_... THC... SEQA Reset K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 General Business Information NXP Semiconductors...
Page 453 1b - Wake-up enabled. Valid from Deep-Sleep. Radio Control AGC (RFP AGC) Interrupt Wake-up 0b - Wake-up disabled. RFP_AGC 1b - Wake-up enabled. Valid from Deep-Sleep. Table continues on the next page... K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 NXP Semiconductors General Business Information...
Page 454 1b - Wake-up enabled. Valid from Deep-Sleep. Digital Microphone (DMIC) Interrupt Wake-up 0b - Wake-up disabled. DMIC 1b - Wake-up enabled. Valid from Deep-Sleep. Table continues on the next page... K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 General Business Information NXP Semiconductors...
Page 455 Field Function RESERVED — Reserved. User software should write zeroes to reserved bits. The value read from a reserved bit is not defined. Table continues on the next page... K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 NXP Semiconductors General Business Information...
Page 456 Writing one to this bit sets the corresponding bit in the STARTER0 register PWM0 Set PWM0_SET Writing one to this bit sets the corresponding bit in the STARTER0 register Table continues on the next page... K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 General Business Information NXP Semiconductors...
Page 457 Writing one to this bit sets the corresponding bit in the STARTER0 register IRBLASTER Set IRBLASTER_S Writing one to this bit sets the corresponding bit in the STARTER0 register Table continues on the next page... K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 NXP Semiconductors General Business Information...
Page 458 D_S... THC... SEQ... Reset Fields Field Function GPIO Set GPIO_SET Writing one to this bit sets the corresponding bit in the STARTER1 register Table continues on the next page... K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 General Business Information NXP Semiconductors...
Page 459 Writing one to this bit sets the corresponding bit in the STARTER1 register M_SET ZIGBEE_MAC Set ZIGBEE_MAC_ Writing one to this bit sets the corresponding bit in the STARTER1 register Table continues on the next page... K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 NXP Semiconductors General Business Information...
Page 460 Reserved. User software should write zeroes to reserved bits. The value read from a reserved bit is not defined. ADC_SEQA Set ADC_SEQA_S Writing one to this bit sets the corresponding bit in the STARTER1 register 2.1.57 Clear STARTER0 Bit Register (STARTERCLR0) Offset Register Offset STARTERCLR0 6C0h K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 General Business Information NXP Semiconductors...
Page 461 Writing one to this bit clears the corresponding bit in the STARTER0 register PWM6 Clear PWM6_CLR Writing one to this bit clears the corresponding bit in the STARTER0 register Table continues on the next page... K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 NXP Semiconductors General Business Information...
Page 462 Writing one to this bit clears the corresponding bit in the STARTER0 register TIMER0 Clear TIMER0_CLR Writing one to this bit clears the corresponding bit in the STARTER0 register Table continues on the next page... K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 General Business Information NXP Semiconductors...
Page 463 Writing one to this bit clears the corresponding bit in the STARTER0 register WDT_BOD Clear WDT_BOD_CL Writing one to this bit clears the corresponding bit in the STARTER0 register 2.1.58 Clear STARTER1 Bits Register (STARTERCLR1) Offset Register Offset STARTERCLR1 6C4h K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 NXP Semiconductors General Business Information...
Page 464 Writing one to this bit clears the corresponding bit in the STARTER1 register ER1_CLR WAKE_UP_TIMER0 Clear WAKE_UP_TIM Writing one to this bit clears the corresponding bit in the STARTER1 register ER0_CLR Table continues on the next page... K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 General Business Information NXP Semiconductors...
Page 465 Writing one to this bit clears the corresponding bit in the STARTER1 register HWVAD Clear HWVAD_CLR Writing one to this bit clears the corresponding bit in the STARTER1 register Table continues on the next page... K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 NXP Semiconductors General Business Information...
Page 466 Writing one to this bit clears the corresponding bit in the STARTER1 register 2.1.59 I/O Retention Control Register (RETENTIONCTRL) Offset Register Offset RETENTIONCTRL 708h Diagram Bits Reserved Reset Bits IOCLA Reserved Reset K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 General Business Information NXP Semiconductors...
Page 467 2.1.60 CPSTACK (CPSTACK) Offset Register Offset CPSTACK 808h Diagram Bits CPSTACK Reset Bits CPSTACK Reset Fields Field Function 31-0 CPSTACK CPSTACK This field should only be modified by the APIs. K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 NXP Semiconductors General Business Information...
Page 468 11b - When COMPINTRLVL = 0 (edge sensitive): both edges (rising and falling); When COMPINTRLVL = 1 (level sensitive): High level Analog Comparator Interrupt Type 0b - Analog Comparator interrupt is edge sensitive. COMPINTRLVL 1b - Analog Comparator interrupt is level sensitive. K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 General Business Information NXP Semiconductors...
Page 469 1b - The voltage on VBAT is not OK, ie. below the BOD threshold. Analog Comparator Status 0b - Comparator in 0 < in 1 ANACOMP 1b - Comparator in 0 > in 1 Table continues on the next page... K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 NXP Semiconductors General Business Information...
Page 470 Function 31-5 RESERVED — Reserved. User software should write zeroes to reserved bits. The value read from a reserved bit is not defined. Table continues on the next page... K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 General Business Information NXP Semiconductors...
Page 471 Writing ones sets the corresponding interrupt enable bits. Note, interrupt enable bits are cleared using ANACTRL_INTENCLR. It requires AHBCLKCTRL0[ANA_INT_CTRL] to be set to use this register. Diagram Bits Reserved Reset Bits BODV ANAC BODV Reserved Reserved BAT... Reset K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 NXP Semiconductors General Business Information...
Page 472 Analog modules (BOD and Analog Comparator) Interrupt Enable Clear register. Writing ones clears the corresponding interrupt enable bits. Note, interrupt enable bits are set in ANACTRL_INTENSET. It requires AHBCLKCTRL0.ANA_INT_CTRL to be set to use this register. K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 General Business Information NXP Semiconductors...
Page 473 Reserved. User software should write zeroes to reserved bits. The value read from a reserved bit is not defined. BOD VBAT Interrupt Enable Clear BODVBAT 2.1.66 Analog Modules Interrupt Status Register (ANACTRL_INTS TAT) Offset Register Offset ANACTRL_INTSTAT A14h K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 NXP Semiconductors General Business Information...
Page 474 Reserved. User software should write zeroes to reserved bits. The value read from a reserved bit is not defined. BOD VBAT Interrupt (after interrupt mask) BODVBAT Only set when ANACTRL_INTENSET[BODVBAT] is enabled. 0b - No interrupt pending. 1b - Interrupt pending. K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 General Business Information NXP Semiconductors...
Page 475 1b - Enabled. Enable XTAL32MHz Clock for Frequency Measure Module 0b - Disabled. XTAL32MHZ_F REQM_ENA 1b - Enabled. Enable Flash 48 MHz Clock 0b - Disabled. FLASH48MHZ_ 1b - Enabled. K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 NXP Semiconductors General Business Information...
Page 476 0b - Disabled. WKT0_CLK_EN 1b - Enabled. Enable Wake-up Timer 1 0b - Disabled. WKT1_ENA 1b - Enabled. Enable Wake-up Timer 0 0b - Disabled. WKT0_ENA 1b - Enabled. K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 General Business Information NXP Semiconductors...
Page 477 Wake-up Timer 0 Reload Value WKT0_LOAD_L Least significant bits ([31:0]). Write when timer is not enabled 2.1.70 Wake-up Timer 0 Reload Value Most Significant Bits Register (WKT_LOAD_WKT0_MSB) Offset Register Offset WKT_LOAD_WKT0_MS A28h K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 NXP Semiconductors General Business Information...
Page 478 Most significant bits ([8:0]). Write when timer is not enabled 2.1.71 Wake-up Timer 1 Reload Value Register (WKT_LOAD_WKT Offset Register Offset WKT_LOAD_WKT1 A2Ch Diagram Bits Reserved WKT1_LOAD Reset Bits WKT1_LOAD Reset K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 General Business Information NXP Semiconductors...
Page 479 Warning: reading is not reliable, read this register several times until you get a stable value. Diagram Bits WKT0_VAL_LSB Reset Bits WKT0_VAL_LSB Reset Fields Field Function 31-0 Wake-up Timer 0 Value WKT0_VAL_LS Least significant bits ([31:0]). Reread until stable value seen. K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 NXP Semiconductors General Business Information...
Page 480 Wake-up Timer 0 Value WKT0_VAL_M Most significant bits ([8:0]). Reread until stable value seen. 2.1.74 Wake-up Timer 1 Current Value Register (WKT_VAL_ WKT1) Offset Register Offset WKT_VAL_WKT1 A38h K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 General Business Information NXP Semiconductors...
Page 481 Reserved. User software should write zeroes to reserved bits. The value read from a reserved bit is not defined. 27-0 Wake-up Timer 1 Value WKT1_VAL Reread until stable value seen. 2.1.75 Wake-up Timers Status Register (WKT_STAT) Offset Register Offset WKT_STAT A3Ch K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 NXP Semiconductors General Business Information...
Page 482 Timeout Status of Wake-up Timer 0 0b - Timeout not reached. WKT0_TIMEOU 1b - Timeout reached. 2.1.76 Interrupt Enable Read and Set Register (WKT_INTENSET) Offset Register Offset WKT_INTENSET A40h K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 General Business Information NXP Semiconductors...
Page 483 Read value of '1' indicates that the interrupt is enabled. Set this bit to enable the interrupt. Use WKT_INTENCLR to disable the interrupt. 2.1.77 Interrupt Enable Clear Register (WKT_INTENCLR) Offset Register Offset WKT_INTENCLR A44h K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 NXP Semiconductors General Business Information...
Page 484 Set this bit to disable the interrupt. Wake-up Timer 0 Timeout Interrupt Enable Clear WKT0_TIMEOU Set this bit to disable the interrupt. 2.1.78 Interrupt Status Register (WKT_INTSTAT) Offset Register Offset WKT_INTSTAT A48h K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 General Business Information NXP Semiconductors...
Page 485 Only set when WKT0_TIMEOUT is enable in INTENSET 0b - No interrupt pending. 1b - Interrupt pending. 2.1.79 GPIO_INT Synchonization First Stage Bypass Register (GPIOPSYNC) Offset Register Offset GPIOPSYNC E08h K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 NXP Semiconductors General Business Information...
Page 486 Enable Bypass of the first stage of synchonization inside GPIO_INT module PSYNC 2.1.80 Chip Revision ID and Number Register (DIEID) Offset Register Offset DIEID FB0h Diagram Bits Reserved MCO_NUM_IN_DIE_ID Reset Bits MCO_NUM_IN_DIE_ID REV_ID Reset K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 General Business Information NXP Semiconductors...
Page 487 2.1.81 Test Access Security Code Register (CODESECURITY PROT) Offset Register Offset CODESECURITYPROT FF0h Function Security code allows test access via SWD/JTAG. Reset with POR, software reset or BOD Diagram Bits SEC_CODE Reset Bits SEC_CODE Reset K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 NXP Semiconductors General Business Information...
Page 488 In some cases, the boot code will secure the device by writing to this register to disable SWD. This would prevent the application being able to re-enable this access. K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 General Business Information NXP Semiconductors...
Page 489 28h - 2Ch I2C specific PIOa Register (PIO_I2C10 - PIO_I2C11) description PIO12 Register (PIO12) description PIO13 Register (PIO13) description PIO14 Register (PIO14) description Table continues on the next page... K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 NXP Semiconductors General Business Information...
Page 490 3.1.2 PIOa Register (PIO0 - PIO21) Offset Register Offset PIO0 PIO1 PIO2 PIO3 PIO4 PIO5 PIO6 PIO7 PIO8 PIO9 PIO12 PIO13 PIO14 PIO15 Table continues on the next page... K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 General Business Information NXP Semiconductors...
Page 491 Before releasing this mode on a wake-up, ensure the IO is set to the required direction and value by using GPIO_DIR and GPIO_PIN registers. Table continues on the next page... K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 NXP Semiconductors General Business Information...
Page 492 EPUN (enable pull-up NOT) input of MFIO pad. 00b - Pull-up resistor enabled. 01b - Repeater mode (bus keeper). 10b - Plain Input. 11b - Pull-down resistor enabled. Table continues on the next page... K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 General Business Information NXP Semiconductors...
Page 493 Function 31-13 RESERVED — Reserved. User software should write zeroes to reserved bits. The value read from a reserved bit is not defined. Table continues on the next page... K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 NXP Semiconductors General Business Information...
Page 494 Pull-up current source enable when set. When IO is in IIC mode (EGP=0) and ECS is low, the IO cell is an open drain cell. Table continues on the next page... K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 General Business Information NXP Semiconductors...
Page 495 GPIO Mode of IO Cell 0b - IIC mode 1b - GPIO mode. Select Digital Function FUNC Select digital function assigned to this pin. 000b GPIO mode 001b-111b See IO MUX. K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 NXP Semiconductors General Business Information...
Page 496 PIO0 PIO21 to the INTPIN bits. For example, setting INTPIN to 0x5 in PINTSEL0 selects pin PIO5 for pin interrupt 0. Each of the pin interrupts must be enabled in the NVIC before it becomes active. K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 General Business Information...
Page 497 With the DMA trigger input mux registers, one trigger input can be selected for each of the DMA channels from the potential internal sources. By default, none of the triggers are selected. K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 NXP Semiconductors...
Page 498 01101b Hash TX 01110b DMA output trigger mux 0 01111b DMA output trigger mux 1 10000b DMA output trigger mux 2 10001b DMA output trigger mux 3 10010b-11111b Reserved K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 General Business Information NXP Semiconductors...
Page 499 DMA Trigger Output for DMA Channel Select which DMA channel output will be used to generate the DMA trigger input, 'DMA Channel Input Mux n'. Values 0 to 18 are valid. K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 NXP Semiconductors General Business Information...
Page 500 Function 31-4 RESERVED — Reserved. User software should write zeroes to reserved bits. The value read from a reserved bit is not defined. Table continues on the next page... K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 General Business Information NXP Semiconductors...
Page 501 Function This register selects a clock for the target clock of the frequency measure function. By default, no clock is selected. Diagram Bits Reserved Reset Bits Reserved CLKIN Reset K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 NXP Semiconductors General Business Information...
Page 502 0101b PIO[4] (must be configured as GPIO) 0110b PIO[20] (must be configured as GPIO) 0111b PIO[16] (must be configured as GPIO) 1000b PIO[15] (must be configured as GPIO) 1001b-1111b Reserved K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 General Business Information NXP Semiconductors...
Page 503 2400h Clear Pin Direction Register (DIRCLR) description 2480h Toggle Pin Direction Register (DIRNOT) description 5.1.2 Byte Pin Register a (B0 - B21) Offset For a = 0 to 21: K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 NXP Semiconductors General Business Information...
Page 504 1000h + (a × 4h) Function There is one register for each PIO. The PIO output value will not affect the IO unless the IO is in GPIO mode. K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 General Business Information NXP Semiconductors...
Page 505 DIRP_ DIRP_ DIRP_ DIRP_ DIRP_ DIRP_ DIRP_ DIRP_ DIRP_ DIRP_ DIRP_ DIRP_ PI... PI... PI... PI... PI... PI... PI... PI... PI... PI... PI... PI... PI... PI... PI... PI... Reset K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 NXP Semiconductors General Business Information...
Page 506 Function 31-22 RESERVED — Reserved. User software should write zeroes to reserved bits. The value read from a reserved bit is not defined. Table continues on the next page... K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 General Business Information NXP Semiconductors...
Page 507 Reads Pinn States or Loads OutpuT 21-0 0b - Read: pin is low; write: clear output bit. PORT_PIOn 1b - Read: pin is high; write: set output bit. K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 NXP Semiconductors General Business Information...
Page 508 1b - Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0. 5.1.8 Set Register (SET) Offset Register Offset 2200h K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 General Business Information NXP Semiconductors...
Page 509 5.1.9 Clear Pin Register Bits Register (CLR) Offset Register Offset 2280h Function Output bits can be cleared by writing ones to these write-only register bits, regardless of MASK register bits. K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 NXP Semiconductors General Business Information...
Page 510 5.1.10 Toggle Pin Register Bits Register (NOT) Offset Register Offset 2300h Function Output bits can be toggled/ inverted/ complemented by writing ones to these write-only register, regardless of MASK register. K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 General Business Information NXP Semiconductors...
Page 511 1b - Toggle output bit. 5.1.11 Set Pin Direction Register (DIRSET) Offset Register Offset DIRSET 2380h Function Direction bits can be set by writing ones to these register bits. K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 NXP Semiconductors General Business Information...
Page 512 1b - Set direction bit. 5.1.12 Clear Pin Direction Register (DIRCLR) Offset Register Offset DIRCLR 2400h Function Direction bits can be cleared by writing ones to these write-only register bits. K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 General Business Information NXP Semiconductors...
Page 513 1b - Clear direction bit 5.1.13 Toggle Pin Direction Register (DIRNOT) Offset Register Offset DIRNOT 2480h Function Direction bits can be set by writing ones to these write-only register bits. K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 NXP Semiconductors General Business Information...
Page 514 Reserved. User software should write zeroes to reserved bits. The value read from a reserved bit is not defined. Toggle PIOn Direction 21-0 0b - No operation. DIRNOTP_PIO 1b - Toggle direction bit. K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 General Business Information NXP Semiconductors...
Page 515 Pin Interrupt Status Register (IST) description Pattern Match Interrupt Control Register (PMCTRL) description Pattern Match Interrupt Bit-slice Source Register (PMSRC) description Pattern Match Interrupt Bit Slice Configuration Register (PMCFG) description K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 NXP Semiconductors General Business Information...
Page 516 Reserved. User software should write zeroes to reserved bits. The value read from a reserved bit is not defined. Pin Interrupt n Interrupt Mode Select PMODE_PINn Selects the interrupt mode for pin interrupt n (selected in PINTSELn). 0b - Edge sensitive. 1b - Level sensitive. K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 General Business Information NXP Semiconductors...
Page 517 Enables the rising edge or level interrupt for pin interrupt n (selected in INPUTMUX_PINTSELn). 0b - Disable rising edge or level interrupt. 1b - Enable rising edge or level interrupt. K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 NXP Semiconductors General Business Information...
Page 518 Reserved. User software should write zeroes to reserved bits. The value read from a reserved bit is not defined. ENRL_PINn Set SETENRL_PIN 1 written to this address set IENR[ENRL_PINn], thus enabling interrupts. 0b - No operation. 1b - Enable rising edge or level interrupt. K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 General Business Information NXP Semiconductors...
Page 519 Reserved. User software should write zeroes to reserved bits. The value read from a reserved bit is not defined. ENRL_PINn Clear CLRENRL_PIN 1 written to this address clear IENR[ENRL_PINn], thus disabling the interrupts. 0b - No operation. 1b - Disable rising edge or level interrupt. K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 NXP Semiconductors General Business Information...
Page 520 Enables the falling edge or configures the active level interrupt for Pin Interrupt n (selected in PINTSELn). 0b - Disable falling edge interrupt or set active interrupt level LOW. 1b - Enable falling edge interrupt enabled or set active interrupt level HIGH. K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 General Business Information NXP Semiconductors...
Page 521 ENAF_PINn Bit Set SETENAF_PIN Ones written to this address set ENAF_PINn in the IENF, thus enabling interrupts. 0b - No operation. 1b - Select HIGH-active interrupt or enable falling edge interrupt. K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 NXP Semiconductors General Business Information...
Page 522 ENAF_PINn Bit Clear CLRENAF_PIN Ones written to this address clears ENAF_PINn in the IENF, thus disabling interrupts. 0b - No operation. 1b - LOW-active interrupt selected or falling edge interrupt disabled. K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 General Business Information NXP Semiconductors...
Page 523 Read 1: a rising edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear rising edge detection status for this pin. K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 NXP Semiconductors General Business Information...
Page 524 Read 1: a falling edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear falling edge detection status for this pin. K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 General Business Information...
Page 525 Write 0: no operation. Read 1: interrupt is being requested for this interrupt pin. Write 1 (edge-sensitive): clear rising- and falling-edge detection for this pin. Write 1 (level-sensitive): switch the active level for this pin (in the IENF register). K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 NXP Semiconductors General Business Information...
Page 526 This field displays the current state of pattern matches. A 1 in any bit of this field indicates that the corresponding product term is matched by the current state of the appropriate inputs. Table continues on the next page... K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 General Business Information NXP Semiconductors...
Page 527 Writing any value to either the PMCFG register or the PMSRC register, or disabling the pattern-match feature (by clearing both the SEL_PMATCH and ENA_RXEV bits in the PMCTRL register to zeros) will erase all edge-detect history. K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 NXP Semiconductors General Business Information...
Page 528 (i.e. where OR terms are to be inserted in the expression). Two types of edge detection on each input are possible: K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 General Business Information...
Page 529 Bits CFG7 CFG6 CFG5 CFG4 CFG3 CFG2 Reset Bits reserv PROD PROD PROD PROD PROD PROD PROD CFG2 CFG1 CFG0 e... _EN... _EN... _EN... _EN... _EN... _EN... _EN... Reset K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 NXP Semiconductors General Business Information...
Page 530 0b - No effect. Slice n is not an endpoint. 1b - Endpoint. Slice n is the endpoint of a product term (minterm). Interrupt PINT0 in the NVIC is raised if the minterm evaluates as true. K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 General Business Information NXP Semiconductors...
Page 531 7.1.2 GPIO Grouped Interrupt Control Register (CTRL) Offset Register Offset CTRL Function Grouped Interrupt (GINT) Interrupt status and configuration settings for the interrupt generation. Diagram Bits Reserved Reset Bits Reserved TRIG COMB Reset K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 NXP Semiconductors General Business Information...
Page 532 POL_ POL_ POL_ POL_ POL_ POL_ POL_ POL_ POL_ POL_ POL_ POL_ PIO... PIO... PIO... PIO... PIO... PIO... PIO9 PIO8 PIO7 PIO6 PIO5 PIO4 PIO3 PIO2 PIO1 PIO0 Reset K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 General Business Information NXP Semiconductors...
Page 533 RESERVED — Reserved. User software should write zeroes to reserved bits. The value read from a reserved bit is not defined. Enable pin PIOn for group interrupt 21-0 ENA_PIOn K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 NXP Semiconductors General Business Information...
Page 534 DMA Channel Interrupt B Status (INTB0) description DMA Channel Set ValidPending Control (SETVALID0) description DMA Channel Set Trigger Control Register (SETTRIG0) description Table continues on the next page... K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 General Business Information NXP Semiconductors...
Page 535 DMA Channel 4 Transfer Configuration Register (XFERCFG4) description 450h Configuration register for DMA channel 5 (CFG5) description 454h DMA Channel 5 Control and Status Register (CTLSTAT5) description Table continues on the next page... K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 NXP Semiconductors General Business Information...
Page 536 DMA Channel 10 Transfer Configuration Register (XFERCFG10) description 4B0h Configuration register for DMA channel 11 (CFG11) description 4B4h DMA Channel 11 Control and Status Register (CTLSTAT11) description Table continues on the next page... K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 General Business Information NXP Semiconductors...
Page 537 DMA Channel 16 Transfer Configuration Register (XFERCFG16) description 510h Configuration register for DMA channel 17 (CFG17) description 514h DMA Channel 17 Control and Status Register (CTLSTAT17) description Table continues on the next page... K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 NXP Semiconductors General Business Information...
Page 538 Function 31-1 RESERVED — Reserved. User software should write zeroes to reserved bits. The value read from a reserved bit is not defined. Table continues on the next page... K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 General Business Information NXP Semiconductors...
Page 539 Function 31-3 RESERVED — Reserved. User software should write zeroes to reserved bits. The value read from a reserved bit is not defined. Table continues on the next page... K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 NXP Semiconductors General Business Information...
Page 540 The SRAMBASE register must be configured with an address (preferably in on-chip SRAM) where DMA descriptors will be stored. Software must set up the descriptors for those DMA channels that will be used in the application. Diagram Bits OFFSET Reset Bits OFFSET Reserved Reset K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 General Business Information NXP Semiconductors...
Page 541 Reserved CH18 CH17 CH16 Reset Bits ENA_ ENA_ ENA_ ENA_ ENA_ ENA_ ENA_ ENA_ ENA_ ENA_ ENA_ ENA_ ENA_ ENA_ ENA_ ENA_ CH15 CH14 CH13 CH12 CH11 CH10 Reset K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 NXP Semiconductors General Business Information...
Page 542 CLR_C CLR_C CLR_C Reserved Reset Bits CLR_ CLR_ CLR_ CLR_ CLR_ CLR_ CLR_ CLR_ CLR_ CLR_ CLR_ CLR_ CLR_ CLR_ CLR_ CLR_ CH15 CH14 CH13 CH12 CH11 CH10 Reset K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 General Business Information NXP Semiconductors...
Page 543 Function 31-19 RESERVED — Reserved. User software should write zeroes to reserved bits. The value read from a reserved bit is not defined. Table continues on the next page... K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 NXP Semiconductors General Business Information...
Page 544 Function 31-19 RESERVED — Reserved. User software should write zeroes to reserved bits. The value read from a reserved bit is not defined. Table continues on the next page... K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 General Business Information NXP Semiconductors...
Page 545 Function 31-19 RESERVED — Reserved. User software should write zeroes to reserved bits. The value read from a reserved bit is not defined. Table continues on the next page... K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 NXP Semiconductors General Business Information...
Page 546 Function 31-19 RESERVED — Reserved. User software should write zeroes to reserved bits. The value read from a reserved bit is not defined. Table continues on the next page... K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 General Business Information NXP Semiconductors...
Page 547 Reserved. User software should write zeroes to reserved bits. The value read from a reserved bit is not defined. 18-0 INTEN_CHn Clear CLR_CHn Writing ones to this register clears INTEN_CHn bits in the INTENSET0. K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 NXP Semiconductors General Business Information...
Page 548 0b - The DMA channel interrupt A is not active. IA_CHn 1b - The DMA channel interrupt A is active. 8.1.13 DMA Channel Interrupt B Status (INTB0) Offset Register Offset INTB0 K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 General Business Information NXP Semiconductors...
Page 549 If, during DMA transmission, a Channel Descriptor is found with XFERCFGn[CFGVALID] set to 0, the DMA checks for a previously buffered SETVALID0 register bit setting for the channel. If found, the DMA will set the descriptor valid, K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 NXP Semiconductors...
Page 550 8.1.15 DMA Channel Set Trigger Control Register (SETTRIG0) Offset Register Offset SETTRIG0 Function The SETTRIG0 register allows setting the CTLSTATn[TRIG] bit in the register for one or more DMA channel. This register is write-only. K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 General Business Information NXP Semiconductors...
Page 551 BUSY0 register. Finally, write a 1 to the proper bit of ABORT0. This prevents the channel from restarting an incomplete operation when it is enabled again. This register is write- only. K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 NXP Semiconductors General Business Information...
Page 552 8.1.17 Configuration register for DMA channel a (CFG0 - CFG18) Offset For a = 0 to 18: Register Offset CFGa 400h + (a × 10h) Function The CFGa register contains various configuration options for DMA channel a. K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 General Business Information NXP Semiconductors...
Page 553 1b - Enabled. Source burst wrapping is enabled for this DMA channel. 13-12 RESERVED — Reserved. The value read from a reserved bit is not defined. Table continues on the next page... K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 NXP Semiconductors General Business Information...
Page 554 0b - Active low - falling edge. Hardware trigger is active low or falling edge triggered, based on TRIGTYPE. 1b - Active high - rising edge. Hardware trigger is active high or rising edge triggered, based on TRIGTYPE. Table continues on the next page... K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 General Business Information NXP Semiconductors...
Page 555 404h + (a × 10h) Function The CTLSTATa register provides status flags specific to DMA channel a. These registers are read-only. Diagram Bits Reserved Reset Bits Reserv VALID Reserved TRIG PE... Reset K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 NXP Semiconductors General Business Information...
Page 556 (the full transfer count has been completed), allowing linked transfers with more than one descriptor to be performed. K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 General Business Information NXP Semiconductors...
Page 557 11b - 4 x width. The destination address is incremented by 4 times the amount specified by Width for each transfer. Table continues on the next page... K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 NXP Semiconductors General Business Information...
Page 558 0b - No effect. 1b - Set. The INTA flag for this channel will be set when the current descriptor is exhausted. Table continues on the next page... K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 General Business Information NXP Semiconductors...
Page 559 (the full transfer count has been completed), allowing linked transfers with more than one descriptor to be performed. K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 NXP Semiconductors General Business Information...
Page 560 11b - 4 x width. The destination address is incremented by 4 times the amount specified by Width for each transfer. Table continues on the next page... K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 General Business Information NXP Semiconductors...
Page 561 0b - No effect. 1b - Set. The INTA flag for this channel will be set when the current descriptor is exhausted. Table continues on the next page... K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 NXP Semiconductors General Business Information...
Page 562 (the full transfer count has been completed), allowing linked transfers with more than one descriptor to be performed. K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 General Business Information NXP Semiconductors...
Page 563 11b - 4 x width. The destination address is incremented by 4 times the amount specified by Width for each transfer. Table continues on the next page... K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 NXP Semiconductors General Business Information...
Page 564 0b - No effect. 1b - Set. The INTA flag for this channel will be set when the current descriptor is exhausted. Table continues on the next page... K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 General Business Information NXP Semiconductors...
Page 565 (the full transfer count has been completed), allowing linked transfers with more than one descriptor to be performed. K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 NXP Semiconductors General Business Information...
Page 566 11b - 4 x width. The destination address is incremented by 4 times the amount specified by Width for each transfer. Table continues on the next page... K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 General Business Information NXP Semiconductors...
Page 567 0b - No effect. 1b - Set. The INTA flag for this channel will be set when the current descriptor is exhausted. Table continues on the next page... K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 NXP Semiconductors General Business Information...
Page 568 (the full transfer count has been completed), allowing linked transfers with more than one descriptor to be performed. K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 General Business Information NXP Semiconductors...
Page 569 11b - 4 x width. The destination address is incremented by 4 times the amount specified by Width for each transfer. Table continues on the next page... K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 NXP Semiconductors General Business Information...
Page 570 0b - No effect. 1b - Set. The INTA flag for this channel will be set when the current descriptor is exhausted. Table continues on the next page... K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 General Business Information NXP Semiconductors...
Page 571 (the full transfer count has been completed), allowing linked transfers with more than one descriptor to be performed. K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 NXP Semiconductors General Business Information...
Page 572 11b - 4 x width. The destination address is incremented by 4 times the amount specified by Width for each transfer. Table continues on the next page... K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 General Business Information NXP Semiconductors...
Page 573 0b - No effect. 1b - Set. The INTA flag for this channel will be set when the current descriptor is exhausted. Table continues on the next page... K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 NXP Semiconductors General Business Information...
Page 574 (the full transfer count has been completed), allowing linked transfers with more than one descriptor to be performed. K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 General Business Information NXP Semiconductors...
Page 575 11b - 4 x width. The destination address is incremented by 4 times the amount specified by Width for each transfer. Table continues on the next page... K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 NXP Semiconductors General Business Information...
Page 576 0b - No effect. 1b - Set. The INTA flag for this channel will be set when the current descriptor is exhausted. Table continues on the next page... K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 General Business Information NXP Semiconductors...
Page 577 (the full transfer count has been completed), allowing linked transfers with more than one descriptor to be performed. K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 NXP Semiconductors General Business Information...
Page 578 11b - 4 x width. The destination address is incremented by 4 times the amount specified by Width for each transfer. Table continues on the next page... K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 General Business Information NXP Semiconductors...
Page 579 0b - No effect. 1b - Set. The INTA flag for this channel will be set when the current descriptor is exhausted. Table continues on the next page... K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 NXP Semiconductors General Business Information...
Page 580 (the full transfer count has been completed), allowing linked transfers with more than one descriptor to be performed. K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 General Business Information NXP Semiconductors...
Page 581 11b - 4 x width. The destination address is incremented by 4 times the amount specified by Width for each transfer. Table continues on the next page... K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 NXP Semiconductors General Business Information...
Page 582 0b - No effect. 1b - Set. The INTA flag for this channel will be set when the current descriptor is exhausted. Table continues on the next page... K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 General Business Information NXP Semiconductors...
Page 583 (the full transfer count has been completed), allowing linked transfers with more than one descriptor to be performed. K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 NXP Semiconductors General Business Information...
Page 584 11b - 4 x width. The destination address is incremented by 4 times the amount specified by Width for each transfer. Table continues on the next page... K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 General Business Information NXP Semiconductors...
Page 585 0b - No effect. 1b - Set. The INTA flag for this channel will be set when the current descriptor is exhausted. Table continues on the next page... K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 NXP Semiconductors General Business Information...
Page 586 (the full transfer count has been completed), allowing linked transfers with more than one descriptor to be performed. K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 General Business Information NXP Semiconductors...
Page 587 11b - 4 x width. The destination address is incremented by 4 times the amount specified by Width for each transfer. Table continues on the next page... K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 NXP Semiconductors General Business Information...
Page 588 0b - No effect. 1b - Set. The INTA flag for this channel will be set when the current descriptor is exhausted. Table continues on the next page... K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 General Business Information NXP Semiconductors...
Page 589 (the full transfer count has been completed), allowing linked transfers with more than one descriptor to be performed. K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 NXP Semiconductors General Business Information...
Page 590 11b - 4 x width. The destination address is incremented by 4 times the amount specified by Width for each transfer. Table continues on the next page... K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 General Business Information NXP Semiconductors...
Page 591 0b - No effect. 1b - Set. The INTA flag for this channel will be set when the current descriptor is exhausted. Table continues on the next page... K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 NXP Semiconductors General Business Information...
Page 592 (the full transfer count has been completed), allowing linked transfers with more than one descriptor to be performed. K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 General Business Information NXP Semiconductors...
Page 593 11b - 4 x width. The destination address is incremented by 4 times the amount specified by Width for each transfer. Table continues on the next page... K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 NXP Semiconductors General Business Information...
Page 594 0b - No effect. 1b - Set. The INTA flag for this channel will be set when the current descriptor is exhausted. Table continues on the next page... K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 General Business Information NXP Semiconductors...
Page 595 (the full transfer count has been completed), allowing linked transfers with more than one descriptor to be performed. K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 NXP Semiconductors General Business Information...
Page 596 11b - 4 x width. The destination address is incremented by 4 times the amount specified by Width for each transfer. Table continues on the next page... K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 General Business Information NXP Semiconductors...
Page 597 0b - No effect. 1b - Set. The INTA flag for this channel will be set when the current descriptor is exhausted. Table continues on the next page... K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 NXP Semiconductors General Business Information...
Page 598 (the full transfer count has been completed), allowing linked transfers with more than one descriptor to be performed. K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 General Business Information NXP Semiconductors...
Page 599 11b - 4 x width. The destination address is incremented by 4 times the amount specified by Width for each transfer. Table continues on the next page... K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 NXP Semiconductors General Business Information...
Page 600 0b - No effect. 1b - Set. The INTA flag for this channel will be set when the current descriptor is exhausted. Table continues on the next page... K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 General Business Information NXP Semiconductors...
Page 601 (the full transfer count has been completed), allowing linked transfers with more than one descriptor to be performed. K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 NXP Semiconductors General Business Information...
Page 602 11b - 4 x width. The destination address is incremented by 4 times the amount specified by Width for each transfer. Table continues on the next page... K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 General Business Information NXP Semiconductors...
Page 603 0b - No effect. 1b - Set. The INTA flag for this channel will be set when the current descriptor is exhausted. Table continues on the next page... K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 NXP Semiconductors General Business Information...
Page 604 (the full transfer count has been completed), allowing linked transfers with more than one descriptor to be performed. K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 General Business Information NXP Semiconductors...
Page 605 11b - 4 x width. The destination address is incremented by 4 times the amount specified by Width for each transfer. Table continues on the next page... K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 NXP Semiconductors General Business Information...
Page 606 0b - No effect. 1b - Set. The INTA flag for this channel will be set when the current descriptor is exhausted. Table continues on the next page... K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 General Business Information NXP Semiconductors...
Page 607 (the full transfer count has been completed), allowing linked transfers with more than one descriptor to be performed. K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 NXP Semiconductors General Business Information...
Page 608 11b - 4 x width. The destination address is incremented by 4 times the amount specified by Width for each transfer. Table continues on the next page... K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 General Business Information NXP Semiconductors...
Page 609 0b - No effect. 1b - Set. The INTA flag for this channel will be set when the current descriptor is exhausted. Table continues on the next page... K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 NXP Semiconductors General Business Information...
Page 610 (the full transfer count has been completed), allowing linked transfers with more than one descriptor to be performed. K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 General Business Information NXP Semiconductors...
Page 611 11b - 4 x width. The destination address is incremented by 4 times the amount specified by Width for each transfer. Table continues on the next page... K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 NXP Semiconductors General Business Information...
Page 612 0b - No effect. 1b - Set. The INTA flag for this channel will be set when the current descriptor is exhausted. Table continues on the next page... K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 General Business Information NXP Semiconductors...
Page 613 0b - Not valid. The channel descriptor is not considered valid until validated by an associated SETVALID0 setting. 1b - Valid. The current channel descriptor is considered valid. K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 NXP Semiconductors General Business Information...
Page 614 PWM Channel 8 Period and Compare register (PCP8) FFFF_FFFFh PWM Channel 9 Period and Compare register (PCP9) FFFF_FFFFh PWM Channel 10 Period and Compare register (PCP10) FFFF_FFFFh Table continues on the next page... K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 General Business Information NXP Semiconductors...
Page 615 Function 31-27 RESERVED — Reserved. User software should write zeroes to reserved bits. The value read from a reserved bit is not defined. Table continues on the next page... K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 NXP Semiconductors General Business Information...
Page 616 DIS_L DIS_L DIS_L Reserved EV... EV... EV... EV... EV... EV... EV... EV... EV... EV... Reset Bits POL_1 Reserved POL_9 POL_8 POL_7 POL_6 POL_5 POL_4 POL_3 POL_2 POL_1 POL_0 Reset K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 General Business Information NXP Semiconductors...
Page 617 PSCL01 Function Each PWM has its own prescaler. This register sets the prescale value for PWM channels 0 and 1. Diagram Bits Reserved PSCL_1 Reset Bits Reserved PSCL_0 Reset K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 NXP Semiconductors General Business Information...
Page 618 PSCL23 Function Each PWM has its own prescaler. This register sets the prescale value for PWM channels 2 and 3. Diagram Bits Reserved PSCL_3 Reset Bits Reserved PSCL_2 Reset K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 General Business Information NXP Semiconductors...
Page 619 PSCL45 Function Each PWM has its own prescaler. This register sets the prescale value for PWM channels 4 and 5. Diagram Bits Reserved PSCL_5 Reset Bits Reserved PSCL_4 Reset K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 NXP Semiconductors General Business Information...
Page 620 PSCL67 Function Each PWM has its own prescaler. This register sets the prescale value for PWM channels 6 and 7. Diagram Bits Reserved PSCL_7 Reset Bits Reserved PSCL_6 Reset K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 General Business Information NXP Semiconductors...
Page 621 PSCL89 Function Each PWM has its own prescaler. This register sets the prescale value for PWM channels 8 and 9. Diagram Bits Reserved PSCL_9 Reset Bits Reserved PSCL_8 Reset K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 NXP Semiconductors General Business Information...
Page 622 Offset Register Offset PSCL10 Function Each PWM has its own prescaler. This register sets the prescale value for PWM channel 10. Diagram Bits Reserved Reset Bits Reserved PSCL_10 Reset K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 General Business Information NXP Semiconductors...
Page 623 PWM channel 0 Compare COMPARE 'COMPARE' must not be 0x0. 15-0 PWM Channel 0 period PERIOD The actual period equals to [PERIOD + 1]. 'PERIOD' must not be 0x0. K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 NXP Semiconductors General Business Information...
Page 624 PERIOD and COMPARE setting for PWM channel 2. Each channel has a counter that counts down from PERIOD to 0. When COMPARE value is reached, PWM output will change on next counter decrement and be stable from 'COMPARE-1' to 0. K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 General Business Information...
Page 625 PERIOD and COMPARE setting for PWM channel 3. Each channel has a counter that counts down from PERIOD to 0. When COMPARE value is reached, PWM output will change on next counter decrement and be stable from 'COMPARE-1' to 0. Diagram Bits COMPARE Reset Bits PERIOD Reset K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 NXP Semiconductors General Business Information...
Page 626 PWM channel 4 Compare COMPARE 'COMPARE' must not be 0x0. 15-0 PWM Channel 4 period PERIOD The actual period equals to [PERIOD + 1]. 'PERIOD' must not be 0x0. K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 General Business Information NXP Semiconductors...
Page 627 PERIOD and COMPARE setting for PWM channel 6. Each channel has a counter that counts down from PERIOD to 0. When COMPARE value is reached, PWM output will change on next counter decrement and be stable from 'COMPARE-1' to 0. K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 NXP Semiconductors...
Page 628 PERIOD and COMPARE setting for PWM channel 7. Each channel has a counter that counts down from PERIOD to 0. When COMPARE value is reached, PWM output will change on next counter decrement and be stable from 'COMPARE-1' to 0. Diagram Bits COMPARE Reset Bits PERIOD Reset K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 General Business Information NXP Semiconductors...
Page 629 PWM channel 8 Compare COMPARE 'COMPARE' must not be 0x0. 15-0 PWM Channel 8 period PERIOD The actual period equals to [PERIOD + 1]. 'PERIOD' must not be 0x0. K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 NXP Semiconductors General Business Information...
Page 630 PERIOD and COMPARE setting for PWM channel 10. Each channel has a counter that counts down from PERIOD to 0. When COMPARE value is reached, PWM output will change on next counter decrement and be stable from 'COMPARE-1' to 0. K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 General Business Information...
Page 631 This register shows the interrupt status for channels 0 to channel 3. The interrupt status can also be cleared with this register. Diagram Bits INT_F INT_F Reserved Reserved LG... LG... Reset Bits INT_F INT_F Reserved Reserved LG... LG... Reset K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 NXP Semiconductors General Business Information...
Page 632 Write 1 to clear the interrupt. 0b - No interrupt pending. 1b - Interrupt pending. 9.1.22 PWM Status Register 1 (Channel 4 to Channel 7) (PST1) Offset Register Offset PST1 K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 General Business Information NXP Semiconductors...
Page 633 Reserved. The value read from a reserved bit is not defined. PWM Channel 5 Interrupt Flag INT_FLG_5 Write 1 to clear the interrupt. 0b - No interrupt pending. 1b - Interrupt pending. Table continues on the next page... K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 NXP Semiconductors General Business Information...
Page 634 Function 31-24 RESERVED — Reserved. User software should write zeroes to reserved bits. The value read from a reserved bit is not defined. Table continues on the next page... K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 General Business Information NXP Semiconductors...
Page 635 Write 1 to clear the interrupt. 0b - No interrupt pending. 1b - Interrupt pending. 9.1.24 PWM Module Identifier Register ('PW' in ASCII) (MODULE_I Offset Register Offset MODULE_ID FFCh K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 NXP Semiconductors General Business Information...
Page 636 Major revision implies software modifications. 11-8 Minor Revision MIN_REV Minor revision without software consequences. Aperture APERTURE Aperture number minus 1 of consecutive packets 4 KB reserved for this IP K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 General Business Information NXP Semiconductors...
Page 637 Capture Control Register (CCR) description Capture Register 0 (CR0) 0000_0000h Capture Register 1 (CR1) 0000_0000h External Match Register (EMR) description Count Control Register (CTCR) description PWM Control Register (PWMC) description K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 NXP Semiconductors General Business Information...
Page 638 Reserved. User software should write zeroes to reserved bits. The value read from a reserved bit is not defined. Interrupt Flag for Capture Channel 1 Event CR1INT Table continues on the next page... K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 General Business Information NXP Semiconductors...
Page 639 Function 31-2 RESERVED — Reserved. User software should write zeroes to reserved bits. The value read from a reserved bit is not defined. Table continues on the next page... K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 NXP Semiconductors General Business Information...
Page 640 0x0000 0000. This event does not cause an interrupt, but a match register can be used to detect an overflow if needed. The TC is controlled through the TCR register. Diagram Bits TCVAL Reset Bits TCVAL Reset K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 General Business Information NXP Semiconductors...
Page 641 TC and clears the PC. Diagram Bits PRVAL Reset Bits PRVAL Reset Fields Field Function Prescale Counter Value 31-0 PRVAL 10.1.6 Prescale Counter Register (PC) Offset Register Offset K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 NXP Semiconductors General Business Information...
Page 642 10.1.7 Match Control Register (MCR) Offset Register Offset Function The Match Control Register is used to control what operations are performed when one of the Match Registers matches the Timer Counter. K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 General Business Information NXP Semiconductors...
Page 643 The TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches the TC. 0b - Disabled. 1b - Enabled. Table continues on the next page... K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 NXP Semiconductors General Business Information...
Page 644 0b - Disabled. 1b - Enabled. Reset on MR0 MR0R The TC will be reset if MR0 matches it. 0b - Disabled. 1b - Enabled. Table continues on the next page... K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 General Business Information NXP Semiconductors...
Page 645 The action possibilities are to generate an interrupt, reset the Timer Counter, or stop the timer. Actions are controlled by the settings in the MCR register. Diagram Bits MATCH Reset Bits MATCH Reset Fields Field Function Timer counter match value. 31-0 MATCH K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 NXP Semiconductors General Business Information...
Page 646 The action possibilities are to generate an interrupt, reset the Timer Counter, or stop the timer. Actions are controlled by the settings in the MCR register. K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 General Business Information...
Page 647 The action possibilities are to generate an interrupt, reset the Timer Counter, or stop the timer. Actions are controlled by the settings in the MCR register. Diagram Bits MATCH Reset Bits MATCH Reset K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 NXP Semiconductors General Business Information...
Page 648 Reserved. User software should write zeroes to reserved bits. The value read from a reserved bit is not defined. Generate Interrupt on Channel 1 Capture Event CAP1I If set, a CR1 load generates an interrupt. Table continues on the next page... K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 General Business Information NXP Semiconductors...
Page 649 The settings in the Capture Control Register (CCR) determine whether the capture function is enabled, and whether a capture event happens on the rising edge, the falling edge, or on both edges of the associated signal. K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 NXP Semiconductors...
Page 650 The settings in the Capture Control Register (CCR) determine whether the capture function is enabled, and whether a capture event happens on the rising edge, the falling edge, or on both edges of the associated signal. Diagram Bits Reset Bits Reset K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 General Business Information NXP Semiconductors...
Page 651 Function 31-12 RESERVED — Reserved. User software should write zeroes to reserved bits. The value read from a reserved bit is not defined. Table continues on the next page... K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 NXP Semiconductors General Business Information...
Page 652 K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 General Business Information NXP Semiconductors...
Page 653 ENCC Setting this bit to 1 enables clearing of the timer and the prescaler when the capture-edge event specified in bits 7:5 occurs. Table continues on the next page... K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 NXP Semiconductors General Business Information...
Page 654 HIGH. The timer is reset by the match register that is configured to set the PWM cycle length. When the timer is reset to zero, all currently HIGH match outputs configured as PWM outputs are cleared. K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 General Business Information...
Page 655 It is recommended to use match channel 3 to set the PWM cycle. 0b - Match. MATn is controlled by EMn. 1b - PWM. PWM mode is enabled for MATn. K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 NXP Semiconductors General Business Information...
Page 656 Function This register contains the basic mode and status of the Watchdog Timer. NOTE A watchdog feed must be performed before any changes to the MOD register take effect. K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 General Business Information NXP Semiconductors...
Page 657 Set when the watchdog timer times out, by a feed error, or by events associated with WDPROTECT. Cleared by software writing a 0 to this bit position. Causes a chip reset if WDRESET = 1. Table continues on the next page... K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 NXP Semiconductors General Business Information...
Page 658 If the MOD[WDPROTECT] = 1, an attempt to change the value of TC before the watchdog counter is below the values of WARNINT[WARNINT] and WINDOW[WINDOW] will cause a watchdog reset and set the MOD[WDTOF] flag. Diagram Bits Reserved COUNT Reset Bits COUNT Reset K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 General Business Information NXP Semiconductors...
Page 659 WDT before control is returned to the interrupted task. Diagram Bits Reserved Reset Bits Reserved FEED Reset K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 NXP Semiconductors General Business Information...
Page 660 6 WDCLK cycles plus 6 APB bus clock cycles, so the value of TV is older than the actual value of the timer when it's being read by the CPU. Diagram Bits Reserved COUNT Reset Bits COUNT Reset K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 General Business Information NXP Semiconductors...
Page 661 Function 31-10 RESERVED — Reserved. User software should write zeroes to reserved bits. The value read from a reserved bit is not defined. Table continues on the next page... K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 NXP Semiconductors General Business Information...
Page 662 TV is greater than the value in WINDOW, a watchdog event will occur. WINDOW resets to the maximum possible TV value, so windowing is not in effect. K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 General Business Information...
Page 663 To wake up the part from deep-sleep mode, enable the RTC interrupts in the system control block SYSCON_STARTER0 register. Diagram Bits Reserved Reset Bits RTC_ RTC1 WAKE ALAR WAKE ALAR Reserv SWRE Reserved KHZ... DPD... MDP... 1KHZ M1HZ Reset K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 NXP Semiconductors General Business Information...
Page 664 (excluding deep power down mode). Writing a 1 clears this bit. RESERVED — Reserved. User software should write zeroes to reserved bits. The value read from a reserved bit is not defined. Table continues on the next page... K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 General Business Information NXP Semiconductors...
Page 665 Match Value MATVAL Contains the match value against which the 1 Hz RTC timer will be compared to generate the alarm flag RTC_ALARM and generate an alarm interrupt/wake-up if enabled. K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 NXP Semiconductors General Business Information...
Page 666 Only write to this register when the CTRL[RTC_EN] bit is 0. The counter increments one second after the CTRL[RTC_EN] bit is set. 12.1.5 16-bit RTC Timer Register (WAKE) Offset Register Offset WAKE K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 General Business Information NXP Semiconductors...
Page 667 A read reflects the current value of 16-bit timer. A write pre-loads a start count value into the 16-bit timer and initializes a count-down sequence. Do not write to this register while counting is in progress. K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 NXP Semiconductors...
Page 668 FIFO Trigger Settings for Interrupt and DMA Request Register (FIFO TRIG) description E10h FIFO Interrupt Enable Set (Enable) and Read Register (FIFOINTE NSET) description Table continues on the next page... K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 General Business Information NXP Semiconductors...
Page 669 2. Disable the USART by writing a 0 to the Enable bit (0 may be written to the entire register). 3. Write the new configuration value, with the ENABLE bit set to 1. K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 NXP Semiconductors...
Page 670 1b - Enabled. When addressing is enabled by ADDRDET, address matching is done by hardware, using the value in the ADDR register as the address to match. Table continues on the next page... K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 General Business Information NXP Semiconductors...
Page 671 1b - Synchronous mode. RESERVED — Reserved. User software should write zeroes to reserved bits. The value read from a reserved bit is not defined. Table continues on the next page... K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 NXP Semiconductors General Business Information...
Page 672 10b - 9 bit data length. The 9th bit is commonly used for addressing in multidrop mode. See the ADDRDET bit in the CTRL regsiter. 11b - Reserved Table continues on the next page... K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 General Business Information NXP Semiconductors...
Page 673 Function USART control settings are more likely to be changed during operation. Diagram Bits AUTO Reserved BAUD Reset Bits CLRC Reserv ADDR TXBR Reserv Reserved TXDIS Reserved CON... Reset K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 NXP Semiconductors General Business Information...
Page 674 This feature can be used to facilitate software flow control. RESERVED — Reserved. User software should write zeroes to reserved bits. The value read from a reserved bit is not defined. Table continues on the next page... K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 General Business Information NXP Semiconductors...
Page 675 INTENCLR register. The error flags for received noise, parity error, and framing error are set immediately upon detection and remain set until cleared by software action in STAT. K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 NXP Semiconductors General Business Information...
Page 676 Receiver Break Detection State Change DELTARXBRK This bit is set when a change in the state of receiver break detection occurs. Cleared by software. Table continues on the next page... K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 General Business Information NXP Semiconductors...
Page 677 1b - Indicate that the receiver is not currently in the process of receiving data. RESERVED — Reserved. User software should write zeroes to reserved bits. The value read from a reserved bit is not defined. K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 NXP Semiconductors General Business Information...
Page 678 When 1, it enables an interrupt when noise is detected. Parity Error Detect Interrupt Enable PARITYERREN When 1, it enables an interrupt when a parity error has been detected. Table continues on the next page... K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 General Business Information NXP Semiconductors...
Page 679 Reserved. User software should write zeroes to reserved bits. The value read from a reserved bit is not defined. RX Ready Interrupt Enable RXRDYEN When 1, it enables an interrupt when RX becomes ready K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 NXP Semiconductors General Business Information...
Page 680 Writing 1 clears the PARITYERR bit in the INTENSET register. FRAMERR Clear FRAMERRCLR Writing 1 clears the FRAMERR bit in the INTENSET register. Table continues on the next page... K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 General Business Information NXP Semiconductors...
Page 681 Reserved. User software should write zeroes to reserved bits. The value read from a reserved bit is not defined. RXRDY Clear RXRDYCLR Writing 1 clears INTENSET[RXRDYEN] bit. 13.1.7 Baud Rate Generator Register (BRG) Offset Register Offset K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 NXP Semiconductors General Business Information...
Page 682 13.1.8 Interrupt Status Register (INTSTAT) Offset Register Offset INTSTAT Function The read-only INTSTAT register provides a view of those interrupt flags that are currently enabled. This can simplify software handling of interrupts. K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 General Business Information NXP Semiconductors...
Page 683 Reserved. User software should write zeroes to reserved bits. The value read from a reserved bit is not defined. Transmitter Disabled Interrupt Flag TXDIS Table continues on the next page... K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 NXP Semiconductors General Business Information...
Page 684 Smaller values of OSR can make the sampling position within a data bit less accurate and may potentially cause more noise errors or incorrect data. K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 General Business Information...
Page 685 13.1.10 Automatic Address Matching Register (ADDR) Offset Register Offset ADDR Function The ADDR register holds the address for hardware address matching in address detect mode with automatic address matching enabled. K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 NXP Semiconductors General Business Information...
Page 686 This register configures FIFO usage. The configuration of PSELID must be performed prior to configuring the FIFO. Diagram Bits POPD EMPT EMPT Reserved Reset Bits SIZE WAKE WAKE DMAR DMAT ENAB ENAB Reserved Reserved LERX LETX Reset K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 General Business Information NXP Semiconductors...
Page 687 1b - Generate a DMA request for the transmit function if the FIFO is not full. Generally, data interrupts would be disabled if DMA is enabled Table continues on the next page... K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 NXP Semiconductors General Business Information...
Page 688 1 to configure the USART functionality. 13.1.12 FIFO Status Register (FIFOSTAT) Offset Register Offset FIFOSTAT E04h Function This register provides status information for the FIFO and also indicates an interrupt from the peripheral function. K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 General Business Information NXP Semiconductors...
Page 689 When 1, the transmit FIFO is not full, so more data can be written. When 0, the transmit FIFO is full and another write would cause it to overflow. Table continues on the next page... K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 NXP Semiconductors General Business Information...
Page 690 Register (FIFOTRIG) Offset Register Offset FIFOTRIG E08h Function This register allows selecting when FIFO-level related interrupts occur. Diagram Bits Reserved RXLVL Reset Bits RXLVL TXLVL Reserved TXLVL Reserved Reset K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 General Business Information NXP Semiconductors...
Page 691 1b - An interrupt will be generated if the receive FIFO level reaches the value specified by the RXLVL field in this register. Table continues on the next page... K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 NXP Semiconductors General Business Information...
Page 692 Function 31-4 RESERVED — Reserved. User software should write zeroes to reserved bits. The value read from a reserved bit is not defined. Table continues on the next page... K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 General Business Information NXP Semiconductors...
Page 693 The FIFOINTENCLR register is used to clear interrupt enable bits in FIFOINTENSET. The complete set of interrupt enables may also be read from this register as well as FIFOINTENSET. K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 NXP Semiconductors General Business Information...
Page 694 Offset FIFOINTSTAT E18h Function The read-only FIFOINTSTAT register provides a view of those interrupt flags that are both pending and currently enabled. This can simplify software handling of interrupts. K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 General Business Information NXP Semiconductors...
Page 695 TX FIFO Error TXERR 13.1.17 FIFO Write Data Register (FIFOWR) Offset Register Offset FIFOWR E20h Function The FIFOWR register is used to write values to be transmitted to the FIFO. K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 NXP Semiconductors General Business Information...
Page 696 The number of bits used depends on the DATALEN. 13.1.18 FIFO Read Data Register (FIFORD) Offset Register Offset FIFORD E30h Function The FIFORD register is used to read values that have been received by the FIFO. K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 General Business Information NXP Semiconductors...
Page 697 Reserved. User software should write zeroes to reserved bits. The value read from a reserved bit is not defined. Received Data from FIFO RXDATA The number of bits used depends on the DATALEN and PARITYSEL settings. K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 NXP Semiconductors General Business Information...
Page 698 This bit reflects the status for the data it is read along with from the FIFO. This bit will be set when a parity error is detected in a received character. Table continues on the next page... K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 General Business Information NXP Semiconductors...
Page 699 13.1.20 Flexcomm ID and Peripheral Function Select Register (PSELID) Offset Register Offset PSELID FF8h Function This register is used to enable the USART FIFO operation. Diagram Bits Reset Bits USAR Reserved Reserved TPR... LOCK PERSEL Reset K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 NXP Semiconductors General Business Information...
Page 700 PERSEL This field is writable by software.010b-111b are reserved. 000b - No peripheral selected. 001b - USART function selected. 13.1.21 USART Module Identifier Register (ID) Offset Register Offset FFCh K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 General Business Information NXP Semiconductors...
Page 701 Major revision implies software modifications 11-8 Minor Revision MIN_REV Minor revision with no software consequences Aperture APERTURE Aperture number minus 1 of consecutive packets 4 Kbytes reserved for this IP K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 NXP Semiconductors General Business Information...
Page 702 FIFO Interrupt Enable Set (enable) and Read Register (FIFOINTE NSET) description E14h FIFO Interrupt Enable Clear (Disable) and Read Register (FIFOINTE NCLR) description E18h FIFO Interrupt Status Register (FIFOINTSTAT) description Table continues on the next page... K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 General Business Information NXP Semiconductors...
Page 703 2. Setup the SPI interface in the CFG register, leaving ENABLE = 0. 3. Enable the FIFO by setting the FIFOCFG[ENABLETX] and FIFOCFG[ENABLERX] bits. 4. Enable the SPI by setting the ENABLE bit in CFG. K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 NXP Semiconductors General Business Information...
Page 704 1b - Enabled. RESERVED — Reserved. User software should write zeroes to reserved bits. The value read from a reserved bit is not defined. Table continues on the next page... K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 General Business Information NXP Semiconductors...
Page 705 Register Offset 404h Function The DLY register controls several programmable delays related to SPI signalling. These delays apply only to master mode, and are all stated in SPI clocks. K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 NXP Semiconductors General Business Information...
Page 706 0000b No additional time is inserted. 0001b 1 SPI clock time is inserted. 0010b 2 SPI clock times are inserted..1111b 15 SPI clock times are inserted. Table continues on the next page... K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 General Business Information NXP Semiconductors...
Page 707 The STAT register provides SPI status flags for software to read, and a control bit for forcing an end of transfer. Flags other than read-only flags may be cleared by writing ones to corresponding bits of STAT. K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 NXP Semiconductors...
Page 708 This allows determining when the SPI transmit/receive functions become busy, and allows waking up the device from reduced power modes when a slave mode access begins. Write 1 to clear this bit. Table continues on the next page... K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 General Business Information NXP Semiconductors...
Page 709 The INTENCLR register is used to clear bits in this register. See STAT register for details of the interrupts. Diagram Bits Reserved Reset Bits MSTID SSDE SSAE TXUR RXOV Reserved Reserved Reserved LE... Reset K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 NXP Semiconductors General Business Information...
Page 710 0b - Disabled. 1b - Enabled. RESERVED — Reserved. User software should write zeroes to reserved bits. The value read from a reserved bit is not defined. K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 General Business Information NXP Semiconductors...
Page 711 Writing 1 clears the SSDEN bit in the INTENSET register. SSAEN Clear SSACLR Writing 1 clears the SSAEN bit in the INTENSET register. Table continues on the next page... K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 NXP Semiconductors General Business Information...
Page 712 Function 31-28 RESERVED — Reserved. User software should write zeroes to reserved bits. The value read from a reserved bit is not defined. Table continues on the next page... K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 General Business Information NXP Semiconductors...
Page 713 Reserved. User software should write zeroes to reserved bits. The value read from a reserved bit is not defined. 14.1.8 SPI Clock Divider Register (DIV) Offset Register Offset 424h Function The DIV register determines the clock used by the SPI in master mode. K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 NXP Semiconductors General Business Information...
Page 714 The read-only INTSTAT register provides a view of those interrupt flags that are currently enabled. This can simplify software handling of interrupts. See STAT for detailed descriptions of the interrupt flags. K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 General Business Information...
Page 715 Transmitter Underrun Interrupt Flag TXUR Receiver Overrun Interrupt Flag RXOV RESERVED — Reserved. User software should write zeroes to reserved bits. The value read from a reserved bit is not defined. K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 NXP Semiconductors General Business Information...
Page 716 When a 1 is written to this bit, the TX FIFO is emptied. 15-14 RESERVED — Reserved. User software should write zeroes to reserved bits. The value read from a reserved bit is not defined. Table continues on the next page... K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 General Business Information NXP Semiconductors...
Page 717 This is automatically enabled when PSELID.PERSEL is set to 2 to configure for SPI functionality 0b - The transmit FIFO is not enabled. 1b - The transmit FIFO is enabled. 14.1.11 FIFO Status Register (FIFOSTAT) Offset Register Offset FIFOSTAT E04h K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 NXP Semiconductors General Business Information...
Page 718 Receive FIFO not empty. When 1, the receive FIFO is not empty, so data can be read. When 0, the receive FIFO is empty. Table continues on the next page... K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 General Business Information NXP Semiconductors...
Page 719 FIFO, or by an underflow if the FIFO is empty when data is needed. Cleared by writing a 1 to this bit. 14.1.12 FIFO Trigger Settings for Interrupt and DMA Request Register (FIFOTRIG) Offset Register Offset FIFOTRIG E08h Function This register allows selecting when FIFO-level related interrupts occur. K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 NXP Semiconductors General Business Information...
Page 720 0111b Trigger when the TX FIFO level decreases to 7 entries (is no longer full). RESERVED — Reserved. User software should write zeroes to reserved bits. The value read from a reserved bit is not defined. Table continues on the next page... K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 General Business Information NXP Semiconductors...
Page 721 Writing ones to implemented bits in this register causes those bits to be set. The FIFOINTENCLR register is used to clear bits in this register. Diagram Bits Reserved Reset Bits RXER TXER Reserved RXLVL TXLVL Reset K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 NXP Semiconductors General Business Information...
Page 722 The FIFOINTENCLR register is used to clear interrupt enable bits in FIFOINTENSET. The complete set of interrupt enables may also be read from this register as well as FIFOINTENSET. K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 General Business Information NXP Semiconductors...
Page 723 The read-only FIFOINTSTAT register provides a view of those interrupt flags that are both pending and currently enabled. This can simplify software handling of interrupts. See FIFOSTAT and FIFOTRIG for details of the interrupts. K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 NXP Semiconductors...
Page 724 TX FIFO Error TXERR 14.1.16 FIFO Write Data Register (FIFOWR) Offset Register Offset FIFOWR E20h Function The FIFOWR register is used to write values to be transmitted to the FIFO. K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 General Business Information NXP Semiconductors...
Page 725 1111b - Data transfer length is 16 bits RESERVED — Reserved. User software should write zeroes to reserved bits. The value read from a reserved bit is not defined. Table continues on the next page... K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 NXP Semiconductors General Business Information...
Page 726 SSEL1 pin is configured by bits in the CFG register. 0b - SSEL1 asserted. 1b - SSEL1 not asserted. Table continues on the next page... K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 General Business Information NXP Semiconductors...
Page 727 Function 31-21 RESERVED — Reserved. User software should write zeroes to reserved bits. The value read from a reserved bit is not defined. Table continues on the next page... K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 NXP Semiconductors General Business Information...
Page 728 This register acts in exactly the same way as FIFORD, except that it supplies data from the top of the FIFO without popping the FIFO (i.e. leaving the FIFO state unchanged). This could be used to allow system software to observe incoming data without interfering with the peripheral driver. K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 General Business Information NXP Semiconductors...
Page 729 SSEL0 pin for both master and slave operation. A zero indicates that a slave select is active. The actual polarity of each slave select pin is configured by the related SPOL bit in CFG. Received Data from FIFO 15-0 RXDATA K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 NXP Semiconductors General Business Information...
Page 730 This field is writable by software. 0 Peripheral select can be changed by software. 1 Peripheral select is locked and cannot be changed until this peripheral or the entire device is reset. Table continues on the next page... K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 General Business Information NXP Semiconductors...
Page 731 Major revision implies software modifications 11-8 Minor Revision MIN_REV Minor revision with no software consequences Aperture APERTURE Aperture number minus 1 of consecutive packets 4 Kbytes reserved for this IP K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 NXP Semiconductors General Business Information...
Page 732 Combined Master Receiver and Transmitter Data Register (MSTD description Slave Control Register (SLVCTL) description Combined Slave Receiver and Transmitter Data Register (SLVDAT) description Slave Address 0 (SLVADR0) description Table continues on the next page... K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 General Business Information NXP Semiconductors...
Page 733 The CFG register contains mode settings that apply to Master, Slave, and Monitor functions. Diagram Bits Reserved Reset Bits HSCA MONC TIMEO MONE SLVE MSTE Reserved PAB... LKS... Reset K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 NXP Semiconductors General Business Information...
Page 734 When disabled, configurations settings for the Slave function are not changed, but the Slave function is internally reset. 0b - Slave function is disabled. 1b - Slave function is enabled. Table continues on the next page... K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 General Business Information NXP Semiconductors...
Page 735 Function 31-26 RESERVED — Reserved. User software should write zeroes to reserved bits. The value read from a reserved bit is not defined. Table continues on the next page... K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 NXP Semiconductors General Business Information...
Page 736 1b - Overrun. A monitor data overrun has occurred. This can only happen when Monitor clock stretching is not enabled via the MOCCLKSTR bit in the CFG register. Writing 1 to this bit clears the flag. Table continues on the next page... K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 General Business Information NXP Semiconductors...
Page 737 01b - Address 1. Slave address 1 was matched. 10b - Address 2. Slave address 2 was matched. 11b - Address 3. Slave address 3 was matched. Table continues on the next page... K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 NXP Semiconductors General Business Information...
Page 738 SLVSTATE field. RESERVED — Reserved. User software should write zeroes to reserved bits. The value read from a reserved bit is not defined. Table continues on the next page... K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 General Business Information NXP Semiconductors...
Page 739 011b - NACK address. Slave NACKed address. 100b - NACK data. Slave NACKed transmitted data. 101b - Reserved. 110b - Reserved. 111b - Reserved. Table continues on the next page... K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 NXP Semiconductors General Business Information...
Page 740 Reserv MONO MONR Reserved Reserved ME... TTI... DLE... DYEN Reset Bits SLVD SLVN SLVPE Reserv MSTS Reserv MSTA MSTP Reserved Reserved Reserved ESE... OTS... ND... TST... RBL... END... Reset K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 General Business Information NXP Semiconductors...
Page 741 1b - Interrupt is enabled. 14-12 RESERVED — Reserved. User software should write zeroes to reserved bits. The value read from a reserved bit is not defined. Table continues on the next page... K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 NXP Semiconductors General Business Information...
Page 742 Reserved. User software should write zeroes to reserved bits. The value read from a reserved bit is not defined. Master Pending Interrupt Enable 0b - Interrupt is disabled. MSTPENDING 1b - Interrupt is enabled. 15.1.5 Interrupt Enable Clear Register (INTENCLR) Offset Register Offset INTENCLR K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 General Business Information NXP Semiconductors...
Page 743 Reserved. User software should write zeroes to reserved bits. The value read from a reserved bit is not defined. Monitor Overrun Interrupt Clear MONOVCLR Table continues on the next page... K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 NXP Semiconductors General Business Information...
Page 744 Master Arbitration Loss Interrupt Clear MSTARBLOSS RESERVED — Reserved. User software should write zeroes to reserved bits. The value read from a reserved bit is not defined. Table continues on the next page... K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 General Business Information NXP Semiconductors...
Page 745 INTENSET[SCLTIMEOUTEN] bit. The SCLTIMEOUT can be used with the SMBus. Diagram Bits Reserved Reset Bits TOMIN Reset K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 NXP Semiconductors General Business Information...
Page 746 I2C-bus specification, some of which are user configured in the MSTTIME register for Master operation. Slave operation uses CLKDIV for some timing functions. Diagram Bits Reserved Reset Bits DIVVAL Reset K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 General Business Information NXP Semiconductors...
Page 747 EVTTI MONI Reserv MONO MONR Reserved Reserved ME... ME... Reset Bits SLVD SLVN SLVPE Reserv MSTS Reserv MSTA MSTP Reserved Reserved Reserved ESEL OTS... ND... TST... RBL... END... Reset K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 NXP Semiconductors General Business Information...
Page 748 Reserved. User software should write zeroes to reserved bits. The value read from a reserved bit is not defined. Slave Pending Interrupt SLVPENDING Table continues on the next page... K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 General Business Information NXP Semiconductors...
Page 749 MSTSTOP or MSTSTART control bit. NOTE When in the idle or slave NACKed states, set the MSTDMA bit either with or after the MSTCONTINUE bit. MSTDMA can be cleared at any time K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 NXP Semiconductors General Business Information...
Page 750 1b - Continue. Informs the Master function to continue to the next operation. This must be done after writing transmit data, reading received data, or other housekeeping related to the next bus operation. K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 General Business Information NXP Semiconductors...
Page 751 MSTSCLHIGH. RESERVED — Reserved. User software should write zeroes to reserved bits. The value read from a reserved bit is not defined. Table continues on the next page... K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 NXP Semiconductors General Business Information...
Page 752 Function 31-8 RESERVED — Reserved. User software should write zeroes to reserved bits. The value read from a reserved bit is not defined. Table continues on the next page... K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 General Business Information NXP Semiconductors...
Page 753 Function 31-10 RESERVED — Reserved. User software should write zeroes to reserved bits. The value read from a reserved bit is not defined. Table continues on the next page... K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 NXP Semiconductors General Business Information...
Page 754 SLVPENDING flag in the STAT register. This must be done after writing transmit data, reading recevied data, or any other housekeeping related to the next bus operation. Automatic Operation has different requirements. SLVCONTINUE should not be set unless SLVPENDING=1. K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 General Business Information NXP Semiconductors...
Page 755 Slave Function Data DATA Read: read the most recently received data for the Slave function. Write: transmit data using the Slave function. 15.1.14 Slave Address 0 (SLVADR0) Offset Register Offset SLVADR0 K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 NXP Semiconductors General Business Information...
Page 756 Seven bit slave address that is compared to received addresses if enabled. The compare can be affected by the setting of the SLVQUAL0 register. Slave Address 0 Disable 0b - Slave Address 0 is enabled. SADISABLE 1b - Slave Address 0 is ignored. K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 General Business Information NXP Semiconductors...
Page 757 Seven bit slave address that is compared to received addresses if enabled. Slave Address 1 Disable 0b - Slave Address 1 is enabled. SADISABLE 1b - Slave Address 1 is ignored. 15.1.16 Slave Address 2 (SLVADR2) Offset Register Offset SLVADR2 K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 NXP Semiconductors General Business Information...
Page 758 1b - Slave Address 2 is ignored. 15.1.17 Slave Address 3 (SLVADR3) Offset Register Offset SLVADR3 Function Slave address register provides for an additional addresses that can be automatically recognized by the I2C slave hardware. K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 General Business Information NXP Semiconductors...
Page 759 1b - Slave Address 3 is ignored. 15.1.18 Slave Qualification for Address 0 (SLVQUAL0) Offset Register Offset SLVQUAL0 Function The SLVQUAL0 register can alter how Slave Address 0 (specified by the SLVADR0 register) is interpreted. K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 NXP Semiconductors General Business Information...
Page 760 MONRXDAT register in time to prevent it, via the CFG[MONCLKSTR] bit. This can help ensure that nothing is missed but can cause the Monitor function to be somewhat intrusive (by potentially adding clock delays, depending on software K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 General Business Information...
Page 761 1b - Start detected. The Monitor function has detected a Start event on the I2C bus. Monitor Function Receiver Data MONRXDAT This reflects every data byte that passes on the I2C pins. K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 NXP Semiconductors General Business Information...
Page 762 There may be software incompatability between major revisions. 11-8 Minor Revision MIN_REV Minor revision with no software consequences Aperture APERTURE Aperture number minus 1 of consecutive packets 4 Kbytes reserved for this IP K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 General Business Information NXP Semiconductors...
Page 763 Pre-Emphasis Filter Coefficient for 2 FS Register 1 (PREAC2FS COEF1) description 12Ch Pre-Emphasis Filter Coefficient for 4 FS Register 1 (PREAC4FS COEF1) description Table continues on the next page... K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 NXP Semiconductors General Business Information...
Page 764 HWVAD Noise Estimator Gain Register (HWVADTHGN) description F94h HWVAD Signal Estimator Gain Register (HWVADTHGS) description F98h HWVAD Noise Envelope Estimator Register (HWVADLOWZ) description FFCh Module Identification Register (ID) 0000_0002h K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 General Business Information NXP Semiconductors...
Page 765 Reserved. Read value is undefined, only zero should be written. Oversample Rate Selection Selects the oversample rate for the related input channel. 16.1.3 DMIC Clock Register a (DIVHFCLK0 - DIVHFCLK1) Offset Register Offset DIVHFCLK0 DIVHFCLK1 124h K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 NXP Semiconductors General Business Information...
Page 766 0111b Divide by 16 1000b Divide by 24 1001b Divide by 32 1010b Divide by 48 1011b Divide by 64 1100b Divide by 96 1101b Divide by 128 Others Reserved K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 General Business Information NXP Semiconductors...
Page 767 Reserved. Read value is undefined, only zero should be written. Pre-emphasis Filer Coefficient for 2 FS Mode 00b - Compensation = 0 COMP 01b - Compensation = -0.16 10b - Compensation = -0.15 11b - Compensation = -0.13 K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 NXP Semiconductors General Business Information...
Page 768 Reserved. Read value is undefined, only zero should be written. Pre-emphasis Filer Coefficient for 4 FS Mode 00b - Compensation = 0 COMP 01b - Compensation = -0.16 10b - Compensation = -0.15 11b - Compensation = -0.13 K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 General Business Information NXP Semiconductors...
Page 769 GAIN Gain control, as a positive or negative (two's complement) number of bits to shift. 16.1.7 FIFO Control Register a (FIFO_CTRL0 - FIFO_CTRL1) Offset Register Offset FIFO_CTRL0 FIFO_CTRL1 1A0h K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 NXP Semiconductors General Business Information...
Page 770 1b - DMA requests based on FIFO level are enabled. Interrupt Enable 0b - FIFO level interrupts are not enabled. INTEN 1b - FIFO level interrupts are enabled. Table continues on the next page... K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 General Business Information NXP Semiconductors...
Page 771 1A4h Function This register provides status information for the FIFO and also indicates an interrupt from the peripheral funcion. Diagram Bits Reserved Reset Bits UNDE OVER RRUN Reserved Reset K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 NXP Semiconductors General Business Information...
Page 772 Register Offset FIFO_DATA0 FIFO_DATA1 1A8h Function This register is used to read values that have been received via the PDM stream. Diagram Bits DATA Reserved Reset Bits DATA Reset K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 General Business Information NXP Semiconductors...
Page 773 Reset Bits PHY_ PHY_F HALF Reserved Reset Fields Field Function 31-2 Reserved — Reserved. Read value is undefined, only zero should be written. Table continues on the next page... K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 NXP Semiconductors General Business Information...
Page 774 16.1.11 DC Control Register a (DC_CTRL0 - DC_CTRL1) Offset Register Offset DC_CTRL0 DC_CTRL1 1B0h Function This register controls the DC filter. Diagram Bits Reserved Reset Bits SATU DCGAIN DCPOLE RAT... Reserved Reserved Reset K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 General Business Information NXP Semiconductors...
Page 775 01b - 155 Hz. 10b - 78 Hz. 11b - 39 Hz. 16.1.12 Channel Enable Register (CHANEN) Offset Register Offset CHANEN F00h Function This register allows enabling either or both PDM channels. K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 NXP Semiconductors General Business Information...
Page 776 Enable Channel 0 EN_CH0 When 1, PDM channel 0 is enabled. 16.1.13 I/O Configuration Register (IOCFG) Offset Register Offset IOCFG F0Ch Function This register configures the use of the PDM pins. K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 General Business Information NXP Semiconductors...
Page 777 When 1, PDM_DATA1 becomes the clock for PDM channel 0. This provides for the possibility of an external codec taking over the PDM bus. 16.1.14 Use 2FS Register (USE2FS) Offset Register Offset USE2FS F10h Function This register allow selecting 2FS output rather than 1FS output. K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 NXP Semiconductors General Business Information...
Page 778 1b - Use 2FS output for PCM data. 16.1.15 HWVAD Input Gain (HWVADGAIN) Offset Register Offset HWVADGAIN F80h Function This register controls the input gain of the HWVAD. Diagram Bits Reserved Reset Bits INPUTGAIN Reserved Reset K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 General Business Information NXP Semiconductors...
Page 779 1100b - 14 bits 1101b - Reserved 1110b - Reserved 1111b - Reserved 16.1.16 HWVAD Filter Control Register (HWVADHPFS) Offset Register Offset HWVADHPFS F84h Function This register controls the HWVAD filter setting. K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 NXP Semiconductors General Business Information...
Page 780 This register controls the operation of the filter block and resets the internal interrut flag. Once the HWVAD triggered an interrupt, a short ‘1’ pulse on bit ST10 clears the interrupt. Keeping the bit on ‘1’ level for some time also has a special function for filter convergence. K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 General Business Information NXP Semiconductors...
Page 781 F8Ch Function Setting bit RSTT to ‘1’ causes a synchronous reset of all filters inside the HVWAD. The RSTT bit must be cleared in order to allow HWVAD operation. K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 NXP Semiconductors General Business Information...
Page 782 Gain value for the noise estimator value. This parameter is used in the following calculation (implemented in hardware): if z8 * (THGS+1) > z7 (THGN+1) HWVAD_RESULT = 1; else HWVAD_RESULT = 0 K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 General Business Information NXP Semiconductors...
Page 783 Gain value for the signal estimator value. This parameter is used in the following calculation (implemented in hardware): if z8 * (THGS+1) > z7 * (THGN+1) HWVAD_RESULT = 1; else HWVAD_RESULT = 0 K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 NXP Semiconductors General Business Information...
Page 784 Values 0 to 14. 0 corresponds to a gain of 1. THGN and THGS are used within the hardware to determine when to assert the HWVAD result. 16.1.21 HWVAD Noise Envelope Estimator Register (HWVADLOW Offset Register Offset HWVADLOWZ F98h Function This register contains of the noise envelop estimator. K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 General Business Information NXP Semiconductors...
Page 785 16.1.22 Module Identification Register (ID) Offset Register Offset FFCh K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 NXP Semiconductors General Business Information...
Page 786 Digital Microphone Interface (DMIC) Diagram Bits Reset Bits Reset Fields Field Function 31-0 Identity Indicate module ID and the number of channels in this DMIC interface. K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 General Business Information NXP Semiconductors...
Page 787 ADC Interrupt Enable Register (INTEN) description ADC Flags Register (FLAGS) description ADC Startup Register (STARTUP) description Second ADC Control Register (GPADC_CTRL0) description Third ADC Control Register (GPADC_CTRL1) description K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 NXP Semiconductors General Business Information...
Page 788 Function 31-15 RESERVED — Reserved. User software should write zeroes to reserved bits. The value read from a reserved bit is not defined. Table continues on the next page... K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 General Business Information NXP Semiconductors...
Page 789 10b - 8-bit resolution. An ADC conversion requires 11 ADC clocks, plus any clocks specified by the TSAMP field. 11b - 6-bit resolution. An ADC conversion requires 9 ADC clocks, plus any clocks specified by the TSAMP field. Table continues on the next page... K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 NXP Semiconductors General Business Information...
Page 790 ADC conversions are controlled through this sequencer which can be used for a single conversion or sets of conversions on one or more channels. Diagram Bits SEQ_ Reserv SINGL BURS STAR SYNC TRIGP MODE Reserved TRIGGER STAR ES... T_B... BYP... Reset Bits TRIGGER Reserved CHANNELS Reset K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 General Business Information NXP Semiconductors...
Page 791 Note that a new sequence could begin just before BURST is cleared. Table continues on the next page... K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 NXP Semiconductors General Business Information...
Page 792 1: A positive edge launches the conversion sequence on the selected trigger input. 0b - 1b - Table continues on the next page... K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 General Business Information NXP Semiconductors...
Page 793 NOTE The method to be employed for each sequence should be reflected in the SEQ_CTRL[MODE] bit since this will impact interrupt and overrun flag generation. K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 NXP Semiconductors General Business Information...
Page 794 0, 0001 channel 1, etc.). 25-20 RESERVED — Reserved. User software should write zeroes to reserved bits. The value read from a reserved bit is not defined. Table continues on the next page... K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 General Business Information NXP Semiconductors...
Page 795 Reserved. User software should write zeroes to reserved bits. The value read from a reserved bit is not defined. 17.1.5 ADC Channel a Data Register (DAT0 - DAT7) Offset For a = 0 to 7: Register Offset DATa 20h + (a × 4h) K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 NXP Semiconductors General Business Information...
Page 796 This bit will contribute to an overrun interrupt/DMA trigger if the SEQ_CTRL[MODE] bit for the corresponding sequence is set to 0 (and if the overrun interrupt is enabled). Table continues on the next page... K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 General Business Information NXP Semiconductors...
Page 797 If less than 12-bit resolultion is used, the ADC result occupies the upper MSBs and unused LSBs should be ignored. RESERVED — Reserved. User software should write zeroes to reserved bits. The value read from a reserved bit is not defined. K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 NXP Semiconductors General Business Information...
Page 798 Reserved. User software should write zeroes to reserved bits. The value read from a reserved bit is not defined. 15-4 Threshold Low THRLOW Low threshold value against which ADC results will be compared Table continues on the next page... K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 General Business Information NXP Semiconductors...
Page 799 INTEN[ADCMPINTENn] bits associated with each channel. THCMPRANGE and THCMPCROSS are channel specific status bits available in the relevant DATn register. Diagram Bits Reserved Reset Bits THRLOW Reserved Reset K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 NXP Semiconductors General Business Information...
Page 800 A threshold crossing event will also generate an interrupt/DMA trigger if enabled to do so via the INTEN[ADCMPINTEN] bits associated with each channel. THCMPRANGE and THCMPCROSS are channel specific status bits available in the relevant DATn register. K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 General Business Information NXP Semiconductors...
Page 801 A threshold crossing event will also generate an interrupt/DMA trigger if enabled to do so via the INTEN[ADCMPINTEN] bits associated with each channel. K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 NXP Semiconductors General Business Information...
Page 802 Reserved. User software should write zeroes to reserved bits. The value read from a reserved bit is not defined. 17.1.10 ADC Channel-Threshold Select Register (CHAN_THRSEL) Offset Register Offset CHAN_THRSEL Function Specifies which set of threshold compare registers are to be used for each channel K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 General Business Information NXP Semiconductors...
Page 803 In this register, threshold events selected in the ADCMPINTENn bits are described as follows: • Disabled: Threshold comparisons on channel n will not generate an ADC threshold-compare interrupt/DMA trigger. K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 NXP Semiconductors General Business Information...
Page 804 Function 31-19 RESERVED — Reserved. User software should write zeroes to reserved bits. The value read from a reserved bit is not defined. Table continues on the next page... K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 General Business Information NXP Semiconductors...
Page 805 A, or upon completion of the entire A sequence of conversions, depending on the MODE bit in the SEQ_CTRL register. 17.1.12 ADC Flags Register (FLAGS) Offset Register Offset FLAGS K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 NXP Semiconductors General Business Information...
Page 806 1s to those bits. RESERVED — Reserved. User software should write zeroes to reserved bits. The value read from a reserved bit is not defined. Table continues on the next page... K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 General Business Information NXP Semiconductors...
Page 807 Offset STARTUP Function This register is typically used only by the ADC API. ADC clock should be selected and running at full frequency prior to writing to this register. K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 NXP Semiconductors General Business Information...
Page 808 A further control register for the ADC that sets the gain mode, can account for the source impedance of signals connecting to the ADC. Additionally, control of the LDO within the ADC sub-system is managed by this register. This will be configured by the software API for the ADC. K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 General Business Information NXP Semiconductors...
Page 809 PASS_ENABLE Test feature only, do not modify this field. LDO Output Select LDO_SEL_OUT Software driver configures correct setting. Do not modify this field. Table continues on the next page... K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 NXP Semiconductors General Business Information...
Page 810 This register controls ADC internal gain and offset. During device test calibration values are calculated to trim the ADC to ensure it meets the device specification. These values are copied into this register by the ADC APIs functions. Diagram Bits Reserved GAIN_CAL Reset Bits GAIN_CAL OFFSET_CAL Reset K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 General Business Information NXP Semiconductors...
Page 811 This field is used within the ADC to compensate for any gain variation for this particular device. Offset Cal OFFSET_CAL This field is used within the ADC to compensate for a DC shift in values for this particular device. K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 NXP Semiconductors General Business Information...
Page 812 FE4h Interrupt Enable Register (INT_ENABLE) description FE8h Clear Interrupt Status Register (INT_CLR_STATUS) description FECh Set Interrupt Status Register (INT_SET_STATUS) description FFCh Controller and Memory Module Identification Register (MODULE_ID) C40F_1500h K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 General Business Information NXP Semiconductors...
Page 813 When a command is executed, it sets appropriate bits in the INT_STATUS registers. Some commands also return additional information in other registers Diagram Bits Reset Bits Reset Fields Field Function 31-0 18.1.3 Event Register (EVENT) Offset Register Offset EVENT K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 NXP Semiconductors General Business Information...
Page 814 When bit is set, the controller wakes up from whatever low power or powerdown mode was active. If not in a powerdown mode, this bit has no effect. Reset When bit is set, the controller and flash are reset. 18.1.4 Auto Programming Register (AUTOPROG) Offset Register Offset AUTOPROG K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 General Business Information NXP Semiconductors...
Page 815 Offset Register Offset STARTA Function Address / Start address for commands that take an address (range) as a parameter. The address is in units of memory words, not bytes. K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 NXP Semiconductors General Business Information...
Page 816 Stop address for commands that take an address range as a parameter (the word specified by STOPA is included in the address range). The address is in units of memory words, not bytes. K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 General Business Information...
Page 817 18.1.7 Data Register a (DATAW0 - DATAW3) Offset Register Offset DATAW0 DATAW1 DATAW2 DATAW3 Function Data register for transfer of data, command parameter or command result up to 128 bits. K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 NXP Semiconductors General Business Information...
Page 818 Used to clear interrupt enable bits. When a INT_CLR_ENABLE bit is written to 1, the corresponding INT_ENABLE bit is cleared. Diagram Bits Reserved Reset Bits ECC_ Reserved DONE FAIL Reset K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 General Business Information NXP Semiconductors...
Page 819 Used to set interrupt enable bits. When a INT_SET_ENABLE bit is written to 1, the corresponding INT_ENABLE bit is set. Diagram Bits Reserved Reset Bits ECC_ Reserved DONE FAIL Reset K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 NXP Semiconductors General Business Information...
Page 820 18.1.10 Interrupt Status Register (INT_STATUS) Offset Register Offset INT_STATUS FE0h Function Used to read the current status of the interrupt status bits. Diagram Bits Reserved Reset Bits ECC_ Reserved DONE FAIL Reset K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 General Business Information NXP Semiconductors...
Page 821 Used to read the current interrupt enable bits. An interrupt is generated where an interrupt is enabled and the corresponding status bit (INT_STATUS) is also set. Diagram Bits Reserved Reset Bits ECC_ Reserved DONE FAIL Reset K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 NXP Semiconductors General Business Information...
Page 822 Used to clear interrupt status bits. When a INT_CLR_STATUS bit is written to 1, the corresponding INT_STATUS bit is cleared. Diagram Bits Reserved Reset Bits ECC_ Reserved DONE FAIL Reset K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 General Business Information NXP Semiconductors...
Page 823 Used to set interrupt status bits. When a INT_SET_STATUS bit is written to 1, the corresponding INT_STATUS bit is set. This can be used to test software by creating status conditions. Diagram Bits Reserved Reset Bits ECC_ Reserved DONE FAIL Reset K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 NXP Semiconductors General Business Information...
Page 824 When a 1 is written to this field, the corresponding INT_STATUS[FAIL] bit is set 18.1.14 Controller and Memory Module Identification Register (MODULE_ID) Offset Register Offset MODULE_ID FFCh Diagram Bits Reset Bits MAJOR_REV MINOR_REV APERTURE Reset K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 General Business Information NXP Semiconductors...
Page 825 Major revision implies software modifications 11-8 Minor Revision MINOR_REV Minor revision with no software consequences Aperture APERTURE Aperture number minus 1 of consecutive packets 4 Kbytes reserved for this IP K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 NXP Semiconductors General Business Information...
Page 826 This register is configured with the operation to perform. The block is enabled once the MODE is selected to any of the available engines (e.g. SHA1, SHA2-256). The operational use is to Write the NEW field to 1, and then data can be pumped into INDATA (and/or its aliases) register. K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 General Business Information NXP Semiconductors...
Page 827 Written 1 to start new hash. It self clears. Note, following the setting of NEW, the WAITING Status bit will clear for a cycle while some initialization occurs. Table continues on the next page... K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 NXP Semiconductors General Business Information...
Page 828 The status register shows when the block is waiting for data and when it has results (which may be partial). These bits correspond to both interrupts and DMA (in the case of data). Diagram Bits Reserved Reset Bits NEEDI NEED Reserv ERRO DIGES WAITI Reserved Reset K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 General Business Information NXP Semiconductors...
Page 829 Offset Register Offset INTENSET Function This register is used to mask-enable interrupt sources to cause processor interrupts. The interrupts can be used for DMA operations or controls over registers. K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 NXP Semiconductors General Business Information...
Page 830 1b - Interrupt when waiting. Write 1 to set this bit. 19.1.5 Interrupt Clear Register (INTENCLR) Offset Register Offset INTENCLR Function The Interrupt Clear register is used to clear interrupts mask-enabled by the INTENSET register. K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 General Business Information NXP Semiconductors...
Page 831 512-bit blocks from Flash or RAM (or whatever system allows) for hashing. The starting location must be word aligned and the length may be up to 128 KB (2K blocks). K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 NXP Semiconductors General Business Information...
Page 832 The MEMADDR register holds the base address for MEMCTRL. It must only point to valid locations per the part (eg. Flash and one or more of the RAMs) and must be word aligned. K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 General Business Information...
Page 833 Input of 16 words at a time to load up buffer. This register is aliased 16 times in the offset range 0x20 to 0x3C which may allow for optimised writing of the data, e.g. using a Store multiple (STM) instruction. Diagram Bits DATA Reset Bits DATA Reset K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 NXP Semiconductors General Business Information...
Page 834 Bits DIGEST Reset Bits DIGEST Reset Fields Field Function 31-0 8 Entry DIGEST/OUTPUT Array DIGEST All 256 bits are valid for SHA2-256. Only 160 bits are valid for SHA1. K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 General Business Information NXP Semiconductors...
Page 835 Offset MASK Diagram Bits MASK Reset Bits MASK Reset Fields Field Function 31-0 MASK MASK Reserved, do not modify this register. 19.1.11 IP Identifier (ID) Offset Register Offset FFCh K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 NXP Semiconductors General Business Information...
Page 836 Major revision implies software modifications 11-8 Minor Revision MIN_REV Minor revision with no software consequences Aperture APERTURE Aperture number minus 1 of consecutive packets 4 KB reserved for this IP K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 General Business Information NXP Semiconductors...
Page 837 20.1.2 SPIFI Control Register (CTRL) Offset Register Offset CTRL Function This register controls the overall operation of the SPIFI, and should be written before any commands are initiated. K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 NXP Semiconductors General Business Information...
Page 838 Cache Prefetching Disable PRFTCH_DIS The SPIFI includes an internal cache. 0b - Enable prefetching of cache lines. 1b - Disable prefetching of cache lines. Table continues on the next page... K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 General Business Information NXP Semiconductors...
Page 839 STAT[CMD] bit. (This allows the flash memory to enter a lower-power state.) If the processor reads data from the flash region after a time-out, the command in the Memory Command (MCMD) Register is issued again. 20.1.3 SPIFI Command Register (CMD) Offset Register Offset K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 NXP Semiconductors General Business Information...
Page 840 01b - Quad/dual data. Data field is quad/dual, other fields are serial. 10b - Serial opcode. Opcode field is serial. Other fields are quad/dual. 11b - All quad/dual. Table continues on the next page... K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 General Business Information NXP Semiconductors...
Page 841 20.1.4 SPIFI Address Register (ADDR) Offset Register Offset ADDR Function Before writing a command that includes an address field to the CMD register, software should write the address to this register. K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 NXP Semiconductors General Business Information...
Page 842 Used as part of the SPIFI operation when required by the command in operation. 20.1.5 SPIFI Intermediate Data Register (IDATA) Offset Register Offset IDATA Function This register is required with some commands. Diagram Bits IDATA Reset Bits IDATA Reset K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 General Business Information NXP Semiconductors...
Page 843 Fields Field Function 31-0 Cache Limit CLIMIT Address accesses above this setting will not get cached in the data cache. 20.1.7 SPIFI Data Register (DATA) Offset Register Offset DATA K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 NXP Semiconductors General Business Information...
Page 844 Function MCMD is used for commands that are accessing the flash memory region of the memory map. Diagram Bits OPCODE FRAMEFORM FIELDFORM INTLEN Reset Bits DOUT POLL Reserved Reset K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 General Business Information NXP Semiconductors...
Page 845 This bit should be written as 0. 13-0 RESERVED — Reserved. User software should write zeroes to reserved bits. The value read from a reserved bit is not defined. K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 NXP Semiconductors General Business Information...
Page 846 Command register. RESERVED — Reserved. User software should write zeroes to reserved bits. The value read from a reserved bit is not defined. Table continues on the next page... K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 General Business Information NXP Semiconductors...
Page 847 This bit is set when software successfully writes the Memory Command register, and is cleared by Reset or by writing a 1 to the RESET bit in this register. K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 NXP Semiconductors General Business Information...
Page 848 Powerdown Mode and Reset Control Register (POWERDOWN) description FFCh IP Identifier Register (MODULEID) A0B8_3200h 21.1.2 Random Number Register (RANDOM_NUMBER) Offset Register Offset RANDOM_NUMBER Function This register is used to access the generated random numbers. K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 General Business Information NXP Semiconductors...
Page 849 21.1.3 Counter Value Register (COUNTER_VAL) Offset Register Offset COUNTER_VAL Function This reigster shows information about the random process. Diagram Bits reserved0 Reset Bits reserved0 REFRESH_CNT CLK_RATIO Reset K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 NXP Semiconductors General Business Information...
Page 850 21.1.4 Counter Configure Register (COUNTER_CFG) Offset Register Offset COUNTER_CFG Function Register linked to the comupting of Statistics, not required for normal operation. Diagram Bits reserved0 Reset Bits reserved0 SHIFT4X CLOCK_SEL MODE Reset K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 General Business Information NXP Semiconductors...
Page 851 10b - Free running: updates countinuously 11b - Reserved 21.1.5 On Line Test Configuration Register (ONLINE_TEST_CFG) Offset Register Offset ONLINE_TEST_CFG Function This register configures settings used in performing the measurements for randomness. K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 NXP Semiconductors General Business Information...
Page 852 (LSB of COUNTER). Otherwise ONLINE_TEST_VAL is updated each time RANDOM_NUMBER is read 21.1.6 Online Test Results Register (ONLINE_TEST_VAL) Offset Register Offset ONLINE_TEST_VAL Function This register is used to access the results of the randomness measurements. K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 General Business Information NXP Semiconductors...
Page 853 This register is used to control reset and active state of the random number generator module. Generally, it is not necessary to use this register. The module is relatively small and so there is normally no need to reset or disable the module. K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 NXP Semiconductors...
Page 854 When used with softreset it forces CORE_RESETN to low on acknowledge from core. _RESET Request Software Reset SOFT_RESET Request softreset that will go low automaticaly after acknowledge from core. 21.1.8 IP Identifier Register (MODULEID) Offset Register Offset MODULEID FFCh K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 General Business Information NXP Semiconductors...
Page 855 Major revision implies software modifications 11-8 Minor Revision MIN_REV Minor revision without software consequences Aperture APERTURE Aperture number minus 1 of consecutive packets 4 KB reserved for this IP K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 NXP Semiconductors General Business Information...
Page 856 Mute card Counter RST High Register (LSB) (MCRH_LSB) description Mute Card Counter RST High Register (MSB) (MCRH_MSB) description UART Receive Register / UART Transmit Register (URR_UTR) 0000_0000h Table continues on the next page... K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 General Business Information NXP Semiconductors...
Page 857 UART Status Register 2 (USR2) description 22.1.2 Slot Select Register (SSR) Offset Register Offset Function This register controls overall reset and enable. Diagram Bits Reserved Reset Bits SEQ_ SOFT Reserved RES... Reset K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 NXP Semiconductors General Business Information...
Page 858 Least significant byte of a 16-bit counter defining the ETU. The ETU counter counts a number of cycles of the Contact Interface clock, this defines the ETU. The minimum acceptable value is 0001 0000b. Diagram Bits Reserved Reset Bits Reserved PDR1_LSB Reset K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 General Business Information NXP Semiconductors...
Page 859 PDR1_MSB Reset Fields Field Function 31-8 RESERVED — Reserved. User software must write zeroes to reserved bits. The value read from a reserved bit is not defined. PDR1_MSB PDR1_MSB K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 NXP Semiconductors General Business Information...
Page 860 Function 31-8 RESERVED — Reserved. User software should write zeroes to reserved bits. The value read from a reserved bit is not defined. Table continues on the next page... K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 General Business Information NXP Semiconductors...
Page 861 FIFO. NOTE In reception mode 00000 = length 1, and in transmission mode 00000 = length 0. K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 NXP Semiconductors General Business Information...
Page 862 In protocol T=0, gtr = FFh means operation at 12 ETUs. Otherwise, operation starts at (12 + gtr ) ETUs, for protocol T=0 or T=1. 22.1.7 Slot 1 UART Configuration Register 1 (UCR11) Offset Register Offset UCR11 K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 General Business Information NXP Semiconductors...
Page 863 The FIFO is flushed during the switching between reception mode and transmission mode, any remaining bytes are lost. 0b - Reception 1b - Transmission Table continues on the next page... K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 NXP Semiconductors General Business Information...
Page 864 UCR21 Function This configuration register defines the reception and transmission settings. Diagram Bits Reserved Reset Bits WRDA FIFOF Reserv DISAT MANB AUTO Reserved DISPE DISFT LU... RC... CON... Reset K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 General Business Information NXP Semiconductors...
Page 865 0, the configuration is automatically detected on the first received character and the bit automatically set after convention detection. 22.1.9 Slot 1 Clock Configuration Register (CCR1) Offset Register Offset CCR1 K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 NXP Semiconductors General Business Information...
Page 866 When set to logic 0, the Contact UART supports asynchronous card. Dynamic change (while activated) is not supported. The choice should be done before activating the card. Table continues on the next page... K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 General Business Information NXP Semiconductors...
Page 867 22.1.10 Power Control Register (PCR) Offset Register Offset Function This configuration register enables to start or stop card sessions Diagram Bits Reserved Reset Bits Reserved RSTIN Reserved WARM START Reset K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 NXP Semiconductors General Business Information...
Page 868 This configuration register enables to program the value of a 8-bit counter used to check whether the card has answered too early. Diagram Bits Reserved Reset Bits Reserved Reset K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 General Business Information NXP Semiconductors...
Page 869 Reserved. User software must write zeroes to reserved bits. The value read from a reserved bit is not defined. Least Significant Byte of Mute Card Counter Value MCRL_LSB A response should be received from the card before the mute card counter expires. K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 NXP Semiconductors General Business Information...
Page 870 The MCRH, mute card reset high, value is a 16-bit value comprised of the {MCRH_MSB, MCRH_LSB} register values and is the mute card timeout setting for use when reset is high. A card should respond before this timeout, otherwise it will be deemed mute. K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 General Business Information NXP Semiconductors...
Page 871 The MCRH, mute card reset high, value is a 16-bit value comprised of the {MCRH_MSB, MCRH_LSB} register values and is the mute card timeout setting for use when reset is high. A card should respond before this timeout, otherwise it will be deemed mute. K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 NXP Semiconductors General Business Information...
Page 872 22.1.16 UART Receive Register / UART Transmit Register (URR_ UTR) Offset Register Offset URR_UTR Function Values written here will be transmiited. Values received over the UART can be read here. K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 General Business Information NXP Semiconductors...
Page 873 This configuration register enables to program the value of a 8-bit ETU counter used to check some timings (CWT, BWT, etc). Exact function depends on settings in TOC. Diagram Bits Reserved Reset Bits Reserved TOR1 Reset K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 NXP Semiconductors General Business Information...
Page 874 Reserved. User software must write zeroes to reserved bits. The value read from a reserved bit is not defined. Timeout Register 2 setting TOR2 This value is used within the timers and timeout functionality of the module. K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 General Business Information NXP Semiconductors...
Page 875 This value is used within the timers and timeout functionality of the module. 22.1.20 Time-Out Configuration Register (TOC) Offset Register Offset Function This configuration register is used for setting different configurations of the time-out counter. K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 NXP Semiconductors General Business Information...
Page 876 Timeout Counter Configuration TOC_CFG Configures the operating mode of the time out counters. 22.1.21 FIFO Status Register (FSR) Offset Register Offset Function This register shows the FIFO fill level. K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 General Business Information NXP Semiconductors...
Page 877 FIFO, otherwise it is the fill level of the receive FIFO. 22.1.22 Mixed Status Register (MSR) Offset Register Offset Function This status register shows the block guard time status. It is intended for polling; it doesn’t generate any interrupt. K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 NXP Semiconductors General Business Information...
Page 878 The bits are set to logic 1 by hardware and set to logic 0 by reading (with a hardware mechanism avoiding the loss of incoming interrupt while reading). K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 General Business Information NXP Semiconductors...
Page 879 FIFO threshold has been passed status bit. In reception, the FIFO contains FTC+1 or more bytes. In transmission, the FIFO contains FTC or less bytes. Status bit is cleared on a read. 22.1.24 UART Status Register 2 (USR2) Offset Register Offset USR2 K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 NXP Semiconductors General Business Information...
Page 880 Reserved. User software must write zeroes to reserved bits. The value read from a reserved bit is not defined. Sequencer Fault Occured. PROT Table continues on the next page... K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 General Business Information NXP Semiconductors...
Page 881 Table continued from the previous page... Field Function RESERVED — Reserved. User software must write zeroes to reserved bits. The value read from a reserved bit is not defined. K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 NXP Semiconductors General Business Information...
Page 882 Analog Interfaces (PMU and Radio) Identity Registers (ANALOGID) description Radio Analog Modules Status Register (RADIOSTATUS) description DC Bus Control (DCBUSCTRL) description Frequency Measure Register (FREQMECTRL) 0000_0000h Table continues on the next page... K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 General Business Information NXP Semiconductors...
Page 883 Function 31-3 RESERVED — Reserved. User software should write zeroes to reserved bits. The value read from a reserved bit is not defined. Table continues on the next page... K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 NXP Semiconductors General Business Information...
Page 884 Set bits in ASYNCPRESETCTRL. Writing ones to this register sets the corresponding bit or bits in the ASYNCPRESETCTRL register, if they are implemented Diagram Bits Reserved Reset Bits CT32B CT32B Reserv Reserved Reset K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 General Business Information NXP Semiconductors...
Page 885 SETCTRLCLR) Offset Register Offset ASYNCPRESETCTRLC Function Clear bits in ASYNCPRESETCTRL. Writing ones to this register clears the corresponding bit or bits in the ASYNCPRESETCTRL register, if they are implemented K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 NXP Semiconductors General Business Information...
Page 886 Reserved. User software should write zeroes to reserved bits. The value read from a reserved bit is not defined. 23.1.5 Asynchronous Peripherals Clock Control Register (ASYN CAPBCLKCTRL) Offset Register Offset ASYNCAPBCLKCTRL K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 General Business Information NXP Semiconductors...
Page 887 Reserved. User software should write zeroes to reserved bits. The value read from a reserved bit is not defined. 23.1.6 ASYNCAPBCLKCTRL Bits Set Register (ASYNCAPBCLKC TRLSET) Offset Register Offset ASYNCAPBCLKCTRLS K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 NXP Semiconductors General Business Information...
Page 888 0b - No effect. 1b - Set the ASYNCAPBCLKCTRL[CT32B0]. RESERVED — Reserved. User software should write zeroes to reserved bits. The value read from a reserved bit is not defined. K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 General Business Information NXP Semiconductors...
Page 889 1b - Clear the ASYNCAPBCLKCTRL[CT32B1]. ASYNCAPBCLKCTRL[CT32B0] Clear CT32B0 Writing 1 to this register clears the ASYNCAPBCLKCTRL[CT32B0]. 0b - No effect. 1b - Clear the ASYNCAPBCLKCTRL[CT32B0]. Table continues on the next page... K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 NXP Semiconductors General Business Information...
Page 890 CTIMER 0/1. 00b - System bus clock 01b - 32 MHz crystal oscillator (XTAL32M). 10b - 32 MHz free running oscillator (FRO32M). 11b - 48 MHz free running oscillator (FRO48M). K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 General Business Information NXP Semiconductors...
Page 891 Reserved. User software should write zeroes to reserved bits. The value read from a reserved bit is not defined. Temperature Sensor Enable 0b - Diabled. ENABLE 1b - Enabled. K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 NXP Semiconductors General Business Information...
Page 892 VDD_EHS1 and VDD_EHS0 set IO cell speed when enabled as an output. It is rcommended to use default value (00b) 00b Low speed. 01b Nominal speed. 10b Fast speed. 11b High speed. Table continues on the next page... K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 General Business Information NXP Semiconductors...
Page 893 1b - Open-drain. Simulated open-drain output (high drive disabled). I2C_SCL IO Driver Slew Rate MSB I2C_SCL_EHS1 Recommended setting is 0 to select slow slew rate. Table continues on the next page... K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 NXP Semiconductors General Business Information...
Page 894 I2C_SDA Receiver Enable Active High I2C_SDA_ENZI I2C_SDA Input Polarity 0b - Input function is not inverted. I2C_SDA_INVE 1b - Input function is inverted. Table continues on the next page... K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 General Business Information NXP Semiconductors...
Page 895 Control of the 32 MHz XTAL LDO. The XTAL will be auto-started on a power-up and settings in SYSCON_XTAL32MCTRL may need modifying before the full control by this register is possible. Diagram Bits Reserved Reset Bits Reserv ENABL Reserv Reserved STABMODE IBIAS VOUT Reset K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 NXP Semiconductors General Business Information...
Page 896 Control of the 32 MHz XTAL. The XTAL will be auto-started on a power-up and settings in SYSCON_XTAL32MCTRL may need modifying before the full control by this register is possible. K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 General Business Information NXP Semiconductors...
Page 897 1b - Enabled 21-18 RESERVED — Reserved. User software should write zeroes to reserved bits. The value read from a reserved bit is not defined. Table continues on the next page... K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 NXP Semiconductors General Business Information...
Page 898 Do not modify contents of this field, managed by API functions. ASS_ENABLE 23.1.13 Analog Interfaces (PMU and Radio) Identity Registers (ANALOGID) Offset Register Offset ANALOGID Diagram Bits Reserved Reset Bits Reserved PMUID Reset K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 General Business Information NXP Semiconductors...
Page 899 The quality of the 32 MHz clock may improve even after this is asserted. Additionally, if settings are changed, such as ibias control, this status flag will probably remain asserted even though changes to the clock signal occur. K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 NXP Semiconductors General Business Information...
Page 900 ADDR[8] should be set to 1 before entering power down to prevent the risk of a small amount of leakage current during power down. This setting is managed within the power APIs. ADDR 23.1.16 Frequency Measure Register (FREQMECTRL) Offset Register Offset FREQMECTRL K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 General Business Information NXP Semiconductors...
Page 901 -1 = 3. The result of SCALE freq_me_plus can be calculated as follows: freq_targetclk =freq_refclk x (CAPVAL+1) / (2 -1). 23.1.17 NFCTAG VDD Output Control Register (NFCTAG_VDD) Offset Register Offset NFCTAG_VDD K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 NXP Semiconductors General Business Information...
Page 902 NFC Tag Vdd IO Output NFCTAG_VDD Output value for the NFC Tag Vdd IO, if enabled with NFCTAG_VDD_OE. _OUT 23.1.18 Full IC Reset Request (from Software application) Register (SWRESETCTRL) Offset Register Offset SWRESETCTRL K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 General Business Information NXP Semiconductors...
Page 903 This bit is only valid if VECTKEY is set correctly. Additionally, the software reset also requires PMC_CTRL[SWRRESETENABLE] to be set. 0b - No effect. 1b - Request a full IC reset level reset. K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 NXP Semiconductors General Business Information...
Page 904 This register Holds the configuration for processing and accepts word, short, and byte access. Must use byte access to write to bits 7:0 in order to avoid resetting parts of the engine. Alternatively, set the configuration when the block is not processing data. K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 General Business Information NXP Semiconductors...
Page 905 11b - Input Text XOR Output Block. 19-18 RESERVED — Reserved. User software should write zeroes to reserved bits. The value read from a reserved bit is not defined. Table continues on the next page... K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 NXP Semiconductors General Business Information...
Page 906 Reserved. User software should write zeroes to reserved bits. The value read from a reserved bit is not defined. GF128 Select Mode 0b - GF128 Hash Input Text. GF128_SEL 1b - GF128 Hash Output Text. Table continues on the next page... K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 General Business Information NXP Semiconductors...
Page 907 Reserved. User software should write zeroes to reserved bits. The value read from a reserved bit is not defined. Wipe WIPE Performs Abort, clear KEY, disable cipher, and clear GF128_Y Table continues on the next page... K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 NXP Semiconductors General Business Information...
Page 908 Secret key is held in OTP and is copied to the AES block by setting this bit. It is necessary to do this after initial powerup, powerdown cycles and internal resets. 24.1.4 Status Register (STAT) Offset Register Offset STAT Function This read only register indicates the status of the AES operations. K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 General Business Information NXP Semiconductors...
Page 909 When set, output Text can be read Input Ready IN_READY When set, input Text can be written Idle IDLE When set, all state machines are idle 24.1.5 Counter Increment Register (CTR_INCR) Offset Register Offset CTR_INCR K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 NXP Semiconductors General Business Information...
Page 910 Offset For a = 0 to 7: Register Offset KEYa 20h + (a × 4h) Function Key [32xa+31:32xa]. The key will be enabled by writing sequentially KEY0, KEY1, KEY2, K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 General Business Information NXP Semiconductors...
Page 911 24.1.7 Input Text a Register (INTEXT0 - INTEXT3) Offset Register Offset INTEXT0 INTEXT1 INTEXT2 INTEXT3 Function Input Text [32xa+31:32xa]. Contains the input data for processing. Typically holds plaintext when encrypting and ciphertext when decrypting K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 NXP Semiconductors General Business Information...
Page 912 24.1.8 Holding a Register (HOLDING0 - HOLDING3) Offset Register Offset HOLDING0 HOLDING1 HOLDING2 HOLDING3 Function Holding [32xa+31:32xa]. Temporary storage used for processing. Begins with Initialization Vector (IV). Diagram Bits HOLDING Reset Bits HOLDING Reset K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 General Business Information NXP Semiconductors...
Page 913 Output Text [32xa+31:32xa]. Contains the output data from processing. Typically holds ciphertext when encrypting and plaintext when decrypting. Diagram Bits OUTTEX Reset Bits OUTTEX Reset Fields Field Function 31-0 OUTTEX K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 NXP Semiconductors General Business Information...
Page 914 GF128 Y [32xa+31:32xa]. Contains Y input of GF128 hash. Diagram Bits GF128_Y Reset Bits GF128_Y Reset Fields Field Function GF128_Y 31-0 GF128_Y 24.1.11 GF128 Za Register (GF128_Z0 - GF128_Z3) Offset Register Offset GF128_Z0 GF128_Z1 GF128_Z2 GF128_Z3 K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 General Business Information NXP Semiconductors...
Page 915 31-0 GF128_Z 24.1.12 GCM Tag a Register (GCM_TAG0 - GCM_TAG3) Offset Register Offset GCM_TAG0 GCM_TAG1 GCM_TAG2 GCM_TAG3 Function GCM Tag [32xa+31:32xa]. Calculated by XORing Output Text and GF128 Z. K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 NXP Semiconductors General Business Information...
Page 916 Advanced Encryption Standard (AES) Diagram Bits GCM_TAG Reset Bits GCM_TAG Reset Fields Field Function GCM_TAG0 31-0 GCM_TAG K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 General Business Information NXP Semiconductors...
Page 917 Interrupt Set Register (INT_SET) description FFCh IR Blaster Module Identifier Register (MODULE_ID) 0131_3000h 25.1.2 Infra-Red Modulator Configuration Register (CONF) Offset Register Offset CONF Function This register configures the Infra-Red Modulator. K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 NXP Semiconductors General Business Information...
Page 918 This is the level of the first envelope after IR Blaster starts or restarts. 0b - First envelope is in low level. 1b - First envelope is in high level. K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 General Business Information NXP Semiconductors...
Page 919 Carrier Time Unit = CTU x TIRCP, TIRCP = IR module clock period, e.g. 1/48 MHz. Value 0x0 is equivalent to 0x1. It is recommended to modify this field when the blaster unit is disabled (i.e when STATUS[ENA_ST] = 0) K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 NXP Semiconductors General Business Information...
Page 920 Envelope duration expressed in carrier period number. T = ENV x (CHIGH + CLOW + 2 ) x CTU. envelope Value 0x000 has the same behaviour as the value 0x001. K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 General Business Information NXP Semiconductors...
Page 921 1b - IR Blaster is enabled IR Blaster FIFO Empty Flag 0b - FIFO is not empty FIFO_EMPTY 1b - FIFO is empty (FIFO level = 000000) Table continues on the next page... K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 NXP Semiconductors General Business Information...
Page 922 25.1.6 Infra-Red Modulator Commands Register (CMD) Offset Register Offset Function This register issues commands to the Infra-Red Modulator, such as Start and Disable. Diagram Bits Reserved Reset Bits FIFO_ Reserved START Reset K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 General Business Information NXP Semiconductors...
Page 923 (the content of the FIFO is conserved). Enable IR Blaster This bit is self clearing. 0b - No effect 1b - Enable IR Blaster 25.1.7 Interrupt Status Register (INT_STATUS) Offset Register Offset INT_STATUS FE0h K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 NXP Semiconductors General Business Information...
Page 924 This interrupt occurs when IR Blaster has started to transmit an envelope with FIFO_IN[ENV_INT] = 1 0b - Interrupt is not pending 1b - Interrupt is pending 25.1.8 Interrupt Enable Register (INT_ENA) Offset Register Offset INT_ENA FE4h K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 General Business Information NXP Semiconductors...
Page 925 This register clears any interrupts that are set in the INT_STATUS register. This is a write only register; write a 1 to a bit location to clear the associated interrupt status flag. K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 NXP Semiconductors...
Page 926 1b - Clear ENV_LAST interrupt Clear ENV_START interrupt ENV_START_C This bit is self clearing. 0b - No effect 1b - Clear ENV_START interrupt 25.1.10 Interrupt Set Register (INT_SET) Offset Register Offset INT_SET FECh K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 General Business Information NXP Semiconductors...
Page 927 This bit is self clearing. 0b - No effect 1b - Set ENV_LAST interrupt Set ENV_START Interrupt ENV_START_S This bit is self clearing. 0b - No effect 1b - Set ENV_START interrupt K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 NXP Semiconductors General Business Information...
Page 928 Major revision implies software modifications. 11-8 Minor Revision MIN_REV Minor revision without software consequences Aperture APERTURE Aperture number minus 1 of consecutive packets 4 KB reserved for this IP. K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 General Business Information NXP Semiconductors...
Page 929 Function 31-2 RESERVED — Reserved. User software should write zeroes to reserved bits. The value read from a reserved bit is not defined. Table continues on the next page... K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 NXP Semiconductors General Business Information...
Page 930 Selection of Antenna ble_ant_selecte ADO is always the inverse of ADE and so is also controlled by this setting as well. 0b - ADE is asserted. 1b - ADE de-asserted. K32W061/K32W041 Register Manual, Rev. 1.1, 06/2020 General Business Information NXP Semiconductors...
Page 932 Information in this document is provided solely to enable system and software implementers to use NXP products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits based on the information in this document. NXP reserves the right to make changes without further notice to any products herein.

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