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The restrictions are described below.
A delay period of about 50 µs from cancellation of a target reset (RESET_IN) to cancellation of a target device
reset (RESET_OUT) (the period from when the target reset (RESET_IN) becomes low to when the target
device reset (RESET_OUT) becomes high) is required for mode setting. See Figure 5-1 below.
A delay fo about 25
(RESET_OUT). See Figure 5-1 below.
RESET_IN
(when shorter than 50 s)
RESET_OUT
RESET_IN
(when longer than 50 s)
RESET_OUT
When setting to on-chip debugging mode via the normal port, without using pins X1 and X2, two of the user
ports will be unavailable for use.
When the user program is downloaded, flash memory programming is performed by self-writing. At that time,
be sure to use a clock that supports the self programming routine's operating frequency range.
A high-level signal is always output from to the FLMD0 pin during emulation. Be sure to connect a pull-down
resistor to the FLMD0 pin, and manipulate this pin based on high/high/impedance levels, rather than on high/low
levels, when using ports for manipulation.
42
CHAPTER 5 RESTRICTIONS
µ
s is required from input of a target reset (RESET_IN) to when the target device is reset
Figure 5-1. Timing of Target Reset
µ
µ
15 s
µ
User's Manual U17029EJ3V0UM
µ
50 s
µ
25 s
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