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TRF7960, TRF7961
SLOU186G – AUGUST 2006 – REVISED MAY 2017
A second counter (12 bits wide) indicates the number of bytes being transmitted (registers 1Dh and 1Eh)
in a data frame. An extension to the transmission-byte counter is a 4-bit broken-byte counter also provided
in register 1Eh (bits B0:B3). Together, these counters make up the TX length value that determines when
the reader generates the EOF byte.
FIFO status flags are as follows:
1. FIFO overflow (bit B4 of register 0x1C) – indicates that the FIFO was loaded too soon
2. FIFO level too low (bit B5 of register 0x1C) – indicates that only 3 bytes are left to be transmitted
(Can be used during transmission.)
3. FIFO level high (bit B6 of register 0x1C) – indicates that 9 bytes are already loaded into the FIFO
(Can be used during reception to generate a FIFO reception IRQ. This is to notify the MCU to service
the reader in time to ensure a continuous data stream.)
During transmission, the FIFO is checked for an almost-empty condition, and during reception, the FIFO is
checked for an almost-full condition. The maximum number of bytes that can be loaded into the FIFO in
one sequence is 12 bytes. The number of bytes in a frame, transmitted or received, can be greater than
12 bytes.
During transmission, the MCU loads the reader FIFO (or during reception, the MCU removes data from
the FIFO), and the FIFO counter counts the number of bytes being loaded into the FIFO. Meanwhile, the
byte counter keeps track of the number of bytes being transmitted. An interrupt request is generated if the
number of bytes in the FIFO is less than 3 or greater than 9, so that the MCU can send new data or
remove the data as necessary. The MCU also checks the number of data bytes to be sent, so as to not
surpass the value defined in TX Length Bytes. The MCU also signals the transmit logic when the last byte
of data is sent or was removed from the FIFO during reception. Transmission starts automatically after the
first byte is written into the FIFO.
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Detailed Description
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TRF7960 TRF7961
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