Texas Instruments TRF7960 Manual page 38

TRF7960, TRF7961
SLOU186G – AUGUST 2006 – REVISED MAY 2017
Write Mode
CKPH – 1, CKPL – 0 (MSP430)
Data Transition – SCLK Falling Edge
MOSI Valid – SCLK Rising Edge
SCLK
MOSI B7
MISO
SS*
The read command is sent out on the MOSI pin, MSB first, in the first eight clock cycles. MOSI data
changes on the falling edge, and is validated in the reader on the rising edge (see
write cycle, the serial data out (MISO) is not valid. After the last read command bit (B0) is validated at the
eighth rising edge of SCLK, after half a clock cycle, valid data can be read on the MISO pin at the falling
edge of SCLK. It takes eight clock edges to read out the full byte (MSB first).
When using the hardware SPI (for example, an MSP430 hardware SPI) to implement this
feature, take care to switch the SCLK polarity after the write phase for proper read operation.
Figure 6-11
Write Mode and Read Mode sections. See the SPI chapter of the family user's guide for any
specific microcontroller family for further information on the setting the appropriate clock
polarity.
This clock polarity switch must be done for all read operations (single or continuous).
The MOSI (serial data out) should not have any transitions (all high or all low) during the read cycle. Also,
the SS* signal should be low during the whole write and read operation.
Figure 6-12 shows the continuous read operation.
38 Detailed Description
Write Address Byte
B6 B5 B4 B3 B2 B1
Don't Care
Figure 6-11. Serial – SPI Communication (Read Mode)
shows the example clock polarity for the MSP430-specific environment in the
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Read Mode
Switch CKPH – 0, CKPL – 0 (MSP430)
SCLK Data Transition – SCLK Rising Edge
Polarity MISO Valid – SCLK Falling Edge
Read Data Byte
No Data Transitions (All High or Low)
B0
B7 B6 B5 B4 B3
NOTE
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B2 B1 B0
Figure 6-11). During the