Texas Instruments TRF7960 Manual page 35

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CLK
I/O_7
I/O_6:I/O_0
Figure 6-6. Parallel Interface Communication With Simple Stop Condition StopSmpl
CLK
I/O_7
I/O_6: I/O_ 0
Figure 6-7. Parallel Interface Communication With Continuous Stop Condition StopCont
6.7.1 Receive
At the start of a receive operation (when SOF is successfully detected), B6 is set in the IRQ Status
register. An interrupt request is sent to the MCU at the end of the receive operation if the receive data
string was shorter than or equal to 8 bytes. The MCU receives the interrupt request, then checks to
determine the reason for the interrupt by reading the IRQ Status register (address 0Ch), after which the
MCU reads the data from the FIFO.
If the received packet is longer than 8 bytes, the interrupt is sent before the end of the receive operation
when the ninth byte is loaded into the FIFO (75% full). The MCU should again read the content of the IRQ
Status register to determine the cause of the interrupt request. If the FIFO is 75% full (as marked with flag
B5 in the IRQ Status register and by reading the FIFO Status register), the MCU should respond by
reading the data from the FIFO to make room for new incoming receive data. When the receive operation
is finished, the interrupt is sent and the MCU must check how many words are still present in the FIFO
before it finishes reading.
If the reader detects a receive error, the corresponding error flag is set (for example, framing error or CRC
error) in the IRQ Status register, which indicates that the MCU reception was completed incorrectly.
6.7.2 Transmit
Before beginning data transmission (see
(0x0F). Data transmission is initiated with a selected command (see
commands the reader to do a continuous write command (3Dh, see
1Dh. Data written into register 1Dh is the TX Length Byte1 (upper and middle nibbles), while the next byte
in register 1Eh is the TX Length Byte2 (lower nibble and broken byte length). The TX byte length
determines when the reader sends the EOF byte. After the TX Length Bytes are written, FIFO data is
loaded in register 1Fh with byte storage locations 0 to 11. Data transmission begins automatically after the
first byte is written into the FIFO. The loading of TX Length Bytes and the FIFO can be done with a
continuous-write command, because the addresses are sequential.
Copyright © 2006–2017, Texas Instruments Incorporated
Start
Condition
50 ns
a1 [7] d1 [7] a2 [7]
a1 [6:0] d1 [6:0] a2 [6:0]
Start
Condition
50 ns
a0 [7] d0 [7]
xx a0 [6:0] d0 [6:0]
Figure
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d2 [7]
d2 [6:0]
d1 [7] d2 [7] d3 [7]
d1 [6:0] d2 [6:0] d3 [6:0]
6-8), the FIFO should be cleared with a reset command
TRF7960 TRF7961
TRF7960, TRF7961
SLOU186G – AUGUST 2006 – REVISED MAY 2017
StopSmpl
Condition
aN [7] dN [7]
aN [6:0] dN [6:0]
StopCont
Condition
dN [7]
dN [6:0] xx
Table 6-31). The MCU then
Table 6-33) starting from register
Detailed Description 35