Texas Instruments TRF7960 Manual page 29

www.ti.com
6.4.3 Status Registers
Table 6-24 describes the IRQ Status register. This register displays the cause of IRQ and TX and RX
status. The default is 0x00 and is reset at POR = H or EN = L and at each write to the ISO Control
register. The register is also automatically set to default at the end of a read phase. This reset also
removes the IRQ flag.
BIT BIT NAME FUNCTION
B7 Irq_tx IRQ set due to end of TX
B6 Irg_srx IRQ set due to RX start
Signals the FIFO is 1/3 > FIFO >
B5 Irq_fifo
2/3
B4 Irq_err1 CRC error
B3 Irq_err2 Parity error
B2 Irq_err3 Byte framing or EOF error
B1 Irq_col Collision error
B0 Irq_noresp No response interrupt
Table 6-25 describes the Collision Position and Interrupt Mask register. The default is 0x3E and is reset at
POR = H and EN = L. Collision bits are reset automatically after a read operation.
Table 6-25. Collision Position and Interrupt Mask Register (Address = 0Dh)
BIT BIT NAME FUNCTION
B7 Col9 Bit position of collision MSB
B6 Col8 Bit position of collision
B5 En_irq_fifo Interrupt enable for FIFO
B4 En_irq_err1 Interrupt enable for CRC
B3 En_irq_err2 Interrupt enable for Parity
Interrupt enable for Framing
B2 En_irq_err3
error or EOF
Interrupt enable for collision
B1 En_irq_col
error
B0 En_irq_noresp Enables no-response interrupt
Table 6-26 describes the Collision Position register. This register displays the bit position of collision or
error. The default is 0x00 and is reset at POR = H and EN = L. Collision bits are reset automatically after a
read operation.
BIT BIT NAME FUNCTION
B7 Col7
B6 Col6
B5 Col5
B4 Col4
Bit position of collision. MSB is B7.
B3 Col3
B2 Col2
B1 Col1
B0 Col0
Copyright © 2006–2017, Texas Instruments Incorporated
Table 6-24. IRQ Status Register (Address = 0Ch)
COMMENTS
Signals that TX is in progress. The flag is set at the start of TX but the
interrupt request is sent when TX is finished.
Signals that RX SOF was received and RX is in progress. The flag is set at
the start of RX but the interrupt request is sent when RX is finished.
Signals FIFO high or low (less than 4 or more than 8)
Indicates receive CRC error
Indicates parity error
Indicates framing error
For ISO/IEC 14443 A and ISO/IEC 15693 single subcarrier
Signal to MCU that next slot command can be sent
COMMENTS
Supported: ISO/IEC 15693, single subcarrier, and ISO/IEC 14443 A
Table 6-26. Collision Position Register (Address = 0Eh)
COMMENTS
Supports ISO/IEC 15693 single subcarrier and ISO/IEC 14443 A. In other
protocols, it shows the bit position of error, either frame, SOF-EOF, parity, or
CRC error.
Submit Documentation Feedback
Product Folder Links:
SLOU186G – AUGUST 2006 – REVISED MAY 2017
TRF7960 TRF7961
TRF7960, TRF7961
Detailed Description 29