Texas Instruments TRF7960 Manual page 39

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Write Address Byte
SCLK
MOSI
B7 B6 B5
MISO
SS*
Special steps are needed to read the TRF796x IRQ Status register (register address 0x0C)
in SPI mode. The status of the bits in this register are cleared after a dummy read. The
following steps must be followed when reading the IRQ Status register.
1. Write command 0x6C: read the IRQ Status register in continuous mode (eight clocks).
2. Read the data in register 0x0C (eight clocks).
3. Generate another eight clocks (as if reading the data in register 0x0D) but ignore the
MISO data line.
See Figure 6-13
SCLK
MOSI
B7
MISO
SS*
Figure 6-13. SPI Communication (IRQ Status Register Read)
6.8.2.1 FIFO Operation
The FIFO is a 12-byte register at address 0x1F with byte storage locations 0 to 11. FIFO data is loaded in
a cyclical manner and can be cleared by a Reset command (0x0F).
Two counters and three FIFO status flags are associated with the FIFO. The first counter is a 4-bit FIFO
byte counter (bits B0 to B3 in register 0x1C) that keeps track of the number of bytes loaded into the FIFO.
If the number of bytes in the FIFO is n, the register value is (n – 1) number of bytes in FIFO register. For
example, if 8 bytes are in the FIFO, the FIFO counter (bits B0 to B3 in register 0x1C) has the value 7.
Copyright © 2006–2017, Texas Instruments Incorporated
Read Data Byte 1
No Data Transitions (All High or Low)
B4 B3 B2 B1 B0
Don't Care B7 B6 B5
Figure 6-12. SPI Communication (Continuous Read Mode)
for an example of this process.
Write Address
Byte (0x6C)
No Data Transitions (All High/Low)
B6 B5 B4 B3 B2 B1 B0
Don't Care B7
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B4 B3 B2 B1 B0
NOTE
Read Data in
IRQ Status Register
No Data Transitions (All High/Low)
B6 B5 B4 B3 B2 B1 B0
TRF7960 TRF7961
TRF7960, TRF7961
SLOU186G – AUGUST 2006 – REVISED MAY 2017
Read Data Byte n
No Data Transitions (All High or Low)
B7 B6 B5 B4 B3 B2 B1 B0
Dummy Read
Ignore
Detailed Description 39