Table of Contents
Advertisement
Philips Semiconductors
2
I
C INTERFACE
P1.3
Input
Filter
P1.3/SDA
Output
Stage
Input
Filter
P1.2/SCL
Output
Stage
P1.2
2003 Dec 8
Bit Counter /
Arbitration &
Sync Logic
Serial Clock
Generator
Timer 1
Overflow
I2CON
Control Register & SCL Duty
I2SCLH
I2SCLL
Status Bus
I2STAT
2
Figure 13: I
C-bus serial interface block diagram
71
Address Register
Comparator
Shift Register
8
Timing
&
Control
Logic
Cycle Registers
Status
Decoder
Status Register
User's Manual - Preliminary -
P89LPC920/921/922
8
I2ADR
ACK
I2DAT
CCLK
Interrupt
8
8
Advertisement
Table of Contents
