Timer Overflow Toggle Output; Timer/Counter 0 Or 1 In Mode 6 (Pwm Auto-Reload) - Philips P89LPC920 User Manual

Philips Semiconductors
TIMERS 0 AND 1
PCLK
TRn
Gate
INTn Pin

Timer overflow toggle output

Timers 0 and 1 can be configured to automatically toggle a port output whenever a timer overflow occurs. The same device pins
that are used for the T0 and T1 count inputs and PWM outputs are also used for the timer toggle outputs. This function is enabled
by control bits ENT0 and ENT1 in the AUXR1 register, and apply to Timer 0 and Timer 1 respectively. The port outputs will be a
logic 1 prior to the first timer overflow when this mode is turned on.In order for this mode to function, the C/T bit must be cleared
selecting PCLK as the clock source for the timer.
2003 Dec 8
C/T = 0
Figure 7-8: Timer/Counter 0 or 1 in Mode 6 (PWM auto-reload)
TLn
(8-bits)
Control
Reload THn on falling transition
and (256-THn) on rising transition
THn
(8-bits)
46
User's Manual - Preliminary -
P89LPC920/921/922
Overflow
TFn
Toggle
ENTn
Interrupt
Tn Pin