Philips P89LPC920 User Manual page 17

Philips Semiconductors
General Description
Notes:
* SFRs are bit addressable.
# SFRs are modified from or added to the 80C51 SFRs.
- Reserved bits, must be written with 0's.
§ BRGR1 and BRGR0 must only be written if BRGEN in BRGCON SFR is '0'. If any of them is written if BRGEN = 1, result is unpredictable.
Unimplemented bits in SFRs (labeled '-' ) are X (unknown) at all times. Unless otherwise specified, ones should not be written to these bits since
they may be used for other purposes in future derivatives. The reset values shown for these bits are '0's although they are unknown when
read.
1. All ports are in input only (high impendance) state after power-up.
2. The RSTSRC register reflects the cause of the LPC920/921/922 reset. Upon a power-up reset, all reset source flags are cleared except POF
and BOF - the power-on reset value is xx110000.
3. After reset, the value is 111001x1, i.e., PRE2-PRE0 are all 1, WDRUN=1 and WDCLK=1. WDTOF bit is 1 after watchdog reset and is 0 after
power-on reset. Other resets will not affect WDTOF.
4. On power-on reset, the TRIM SFR is initialized with a factory preprogrammed value. Other resets will not cause initialization of the TRIM
register.
5. The only reset source that affects these SFRs is power-on reset.
2003 Dec 8
17
User's Manual - Preliminary -
P89LPC920/921/922