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Philips Semiconductors
UART
S1...S16 S1...S16 S1...S16
Write to SBUF
Shift
RxD (Data Out)
TxD (Shift Clock)
TI
Write to SCON (Clear RI)
RI
Shift
RxD
(Data In)
TxD (Shift Clock)
More about UART Mode 1
Reception is initiated by detecting a 1-to-0 transition on RxD. RxD is sampled at a rate 16 times the programmed baud rate. When
a transition is detected, the divide-by-16 counter is immediately reset. Each bit time is thus divided into 16 counter states. At the
7th, 8th, and 9th counter states, the bit detector samples the value of RxD. The value accepted is the value that was seen in at
least 2 of the 3 samples. This is done for noise rejection. If the value accepted during the first bit time is not 0, the receive circuits
are reset and the receiver goes back to looking for another 1-to-0 transition. This provides rejection of false start bits. If the start
bit proves valid, it is shifted into the input shift register, and reception of the rest of the frame will proceed.
The signal to load SBUF and RB8, and to set RI, will be generated if, and only if, the following conditions are met at the time the
final shift pulse is generated: RI = 0 and either SM2=0 or the received stop bit =1. If either of these two conditions is not met, the
received frame is lost. If both conditions are met, the stop bit goes into RB8, the 8 data bits go into SBUF, and RI is activated.
TX Clock
Write to SBUF
Shift
TxD
TI
RX Clock
RxD
÷ 16 Reset
Shift
RI
Figure 9-6: Serial Port Mode 1 (only single transmit buffering case is shown)
2003 Dec 8
S1...S16
S1...S16
S1...S16 S1...S16 S1...S16
D0
D1
D2
D0
D1
Figure 9-5: Serial Port Mode 0 (double buffering must be disabled)
Start Bit
D0
D1
D2
Start Bit
D0
D1
D2
S1...S16
S1...S16
D3
D4
D5
D6
D2
D3
D4
D5
D3
D4
D5
D3
D4
D5
56
User's Manual - Preliminary -
P89LPC920/921/922
S1...S16
S1...S16
S1...S16
D7
D6
D7
D6
D7
Stop Bit
INTLO = 0
INTLO = 1
D6
D7
Stop Bit
Transmit
Receive
Transmit
Receive
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