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Philips Semiconductors
CLOCKS
External clock input option
In this configuration, the processor clock is derived from an external source driving the XTAL1 / P3.1 pin. The rate may be from
0 Hz up to 12 MHz. The XTAL2 / P3.0 pin may be used as a standard port pin or a clock output.
High freq.
XTAL1
Med freq.
XTAL2
Low freq.
RC Oscillator
(7.3728MHz)
W atchdog
Oscillator
(400KHz)
Baud Rate
Generator
Oscillator Clock (OSCCLK) wakeup delay
The P89LPC920/921/922 has an internal wakeup timer that delays the clock until it stabilizes depending to the clock source used.
If the clock source is any of the three crystal selections, the delay is 992 OSCCLK cycles plus 60-100µs. If the clock source is
either the internal RC oscillator or the Watchdog oscillator, the delay is 224 OSCCLK cycles plus 60-100µs.
CPU Clock (CCLK) modification: DIVM register
The OSCCLK frequency can be divided down, by an integer, up to 510 times by configuring a dividing register, DIVM, to provide
CCLK. This produces the CCLK frequency using the following formula:
CCLK frequency = f
Where: f
is the frequency of OSCCLK
OSC
N is the value of DIVM.
Since N ranges from 0 to 255, the CCLK frequency can be in the range of f
This feature makes it possible to temporarily run the CPU at a lower rate, reducing power consumption. By dividing the clock, the
CPU can retain the ability to respond to events other than those that can cause interrupts (i.e. events that allow exiting the Idle
mode) by executing its normal program at a lower rate. This can often result in lower power consumption than in Idle mode. This
2003 Dec 8
FOSC2:0
UART
Figure 2-3: Block diagram of oscillator control
/ (2N)
OSC
CPU
Clock
OSC
CCLK
CLK
DIVM
/2
Timer 0 & 1
to f
OSC
23
User's Manual - Preliminary -
P89LPC920/921/922
RTCS1:0
PCLK
Peripheral Clock
/510. (for N =0, CCLK = f
OSC
RTC
CPU
W DT
I
C
2
) .
OSC
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