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Philips Semiconductors
2
I
C INTERFACE
The STA bit is START flag. Setting this bit causes the I
condition or transmitting a repeated START condition when it is already in master mode.
The STO bit is STOP flag. Setting this bit causes the I
from an error condition in slave mode.
If the STA and STO are both set, then a STOP condition is transmitted to the I
START condition afterwards. If it is in slave mode, an internal STOP condition will be generated, but it is not transmitted to the
bus.
I2CON
Address: D8h
Bit addressable
Reset Source(s): Any reset
Reset Value: x00000x0B
BIT
SYMBOL
I2CON.7
-
I2CON.6
I2EN
I2CON.5
STA
I2CON.4
STO
I2CON.3
SI
I2CON.2
AA
I2CON.1
-
I2CON.0
CRSEL
2003 Dec 8
2
C interface to enter master mode and attempt transmitting a START
2
C interface to transmit a STOP condition in master mode, or recovering
7
6
-
I2EN
STA
FUNCTION
Reserved for future use. Should not be set to 1 by user programs.
2
I
C Interface Enable. When set, enables the I
disabled.
2
Start Flag. STA = 1: I
C enters master mode, checks the bus and generates a START
condition if the bus is free. If the bus is not free, it waits for a STOP condition (which will
free the bus) and generates a START condition after a delay of a half clock period of the
internal clock generator. When the I
is transmitted or received, it transmits a repeated START condition. STA may be set at
any time, it may also be set when the I
STA = 0: no START condition or repeated START condition will be generated.
STOP Flag. STO = 1: In master mode, a STOP condition is transmitted to the I
When the bus detects the STOP condition, it will clear STO bit automatically.
In slave mode, setting this bit can recover from an error condition. In this case, no STOP
condition is transmitted to the bus. The hardware behaves as if a STOP condition has
been received and it switches to "not addressed" Slave Receiver Mode. The STO flag is
cleared by hardware automatically.
2
I
C Interrupt Flag. This bit is set when one of the 25 possible I
When EA bit and EI2C (IEN1.0) bit are both set, an interrupt is requested when SI is set..
Must be cleared by software by writing 0 to this bit.
The Assert Acknowledge Flag. When set to 1, an acknowledge (low level to SDA) will be
returned during the acknowledge clock pulse on the SCL line on the following situations:
(1)The "own slave address" has been received. (2)The general call address has been
received while the general call bit(GC) in I2ADR is set. (3) A data byte has been received
2
while the I
C interface is in the Master Receiver Mode. (4)A data byte has been received
2
while the I
C interface is in the addressed Slave Receiver Mode
When cleared to 0, an not acknowledge (high level to SDA) will be returned during the
acknowledge clock pulse on the SCL line on the following situations: (1) A data byte has
2
been received while the I
C interface is in the Master Receiver Mode. (2) A data byte has
2
been received while the I
C interface is in the addressed Slave Receiver Mode.
Reserved for future use. Should not be set to 1 by user programs.
SCL clock selection. When set = 1, Timer1 overflow generates SCL, when cleared = 0,
the internal SCL generator is used base on values of I2SCLH and I2SCLL.
2
Figure 4: I
C Control register
2
C-bus if it is in master mode, and transmits a
5
4
3
STO
SI
2
C interface. When clear, the I
2
C interface is already in master mode and some data
2
C interface is in an addressed slave mode.
65
User's Manual - Preliminary -
P89LPC920/921/922
2
1
0
AA
-
CRSEL
2
C function is
2
C-bus.
2
C states is entered.
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