Table of Contents
Advertisement
Quick Links
Advertisement
Table of Contents
Related Manuals for Tews Technologies TPMC321
Summary of Contents for Tews Technologies TPMC321
- Page 1 Conducion cooled 64 Digital TTL I/O / 32 Differential I/O Version 1.0 User Manual Issue 1.0.0 April 2022 TEWS TECHNOLOGIES GmbH Am Bahnhof 7 25469 Halstenbek, Germany Phone: +49 (0) 4101 4058 0 Fax: +49 (0) 4101 4058 19 e-mail: info@tews.com...
- Page 2 (RoHS compliant) TPMC321-12R TEWS TECHNOLOGIES GmbH is not liable for any damage arising out of the application or use of the Conduction Cooled, 32-bit M-LVDS I/O, Bit I/O, device described herein.
- Page 3 Issue Description Date 1.0.0 Initial issue April 2022 TPMC321 User Manual Issue 1.0.0 Page 3 of 33...
-
Page 4: Table Of Contents
6.1.2 TTL Buffer Pull Up Voltage ..................... 31 Differential I/O-Interface ....................... 31 Optional P14 Ground Connections ..................... 32 PIN ASSIGNMENT – I/O CONNECTOR ..............33 P14 Back I/O Connector ....................... 33 TPMC321 User Manual Issue 1.0.0 Page 4 of 33... - Page 5 TABLE 8-16: NEGATIVE EDGE INTERRUPT ENABLE REGISTER 0 (NIER0) ..........27 TABLE 8-17: NEGATIVE EDGE INTERRUPT ENABLE REGISTER 1 (NIER1) ..........28 TABLE 8-18: REVISION REGISTER (FREVREG) ..................29 TABLE 5-1 : P14 BACK I/O CONNECTOR ..................... 33 TPMC321 User Manual Issue 1.0.0 Page 5 of 33...
-
Page 6: Product Description
1 Product Description The TPMC321 is a conduction cooled single-width 32 bit PMC module offering 64 ESD-protected 5V-tolerant TTL lines or 32 differential I/O lines using ESD-protected EIA-422 / EIA-485 compatible line transceivers or Multipoint-LVDS transceivers. Each line is individually programmable as input, output or tri-state. The receivers are always enabled, which allows determining the state of each I/O line at any time. -
Page 7: Technical Specification
If FIT rates are not available, MIL-HDBK-217F and MIL-HDBK-217F Notice 2 formulas are used for FIT rate calculation. Humidity 5 – 95 % non-condensing Weight 53 g Table 2-1 : Technical Specification TPMC321 User Manual Issue 1.0.0 Page 7 of 33... -
Page 8: Handling And Operation Instructions
3 Handling and Operation Instructions ESD Protection This PMC module is sensitive to static electricity. Packing, unpacking and all other module handling has to be done with appropriate care. TPMC321 User Manual Issue 1.0.0 Page 8 of 33... -
Page 9: Terms And Definitions
For future software compatibility: For register write access reserved bits shall be written ‘0’. Style Conventions Hexadecimal characters are specified with prefix 0x (i.e. 0x029E). For signals on hardware products, "Active Low" is represented by the signal name with an added # (i.e. IP_RESET#). TPMC321 User Manual Issue 1.0.0 Page 9 of 33... -
Page 10: Pci Interface
1 (0x14) Little 2 (0x18) BIG *) Functional Register Space Table 5-2 : PCI Base Address Registers *) Can be configured in the “Functional Register Space Descriptor (LAS0BRD)” register. Default is BIG. TPMC321 User Manual Issue 1.0.0 Page 10 of 33... -
Page 11: Register Map
5.3.2.1 Functional Register Space Descriptor (LAS0BRD) Reset Symbol Description Access Value 31:25 Reserved ASBYTE_ORDER Address Space Byte Ordering 1: activate Big Endian 0: activate Little Endian 23:0 Reserved Table 5-4 : Functional Register Space Descriptor (LAS0BRD) TPMC321 User Manual Issue 1.0.0 Page 11 of 33... -
Page 12: Interrupt Control/Status (Intcsr)
1: adjusts active high polarity 0: adjusts active low polarity LINT_EN Local Interrupt (LINTi1) Enable 1: enables Local Control Logic interrupts 0: disables Local Control Logic interrupts Table 5-5 : Interrupt Control/Status (INTCSR) TPMC321 User Manual Issue 1.0.0 Page 12 of 33... -
Page 13: Serial Eeprom And Initialization Control (Cntrl)
1: asserts serial EEPROM chip select 0: de-asserts serial EEPROM chip select EESK Serial EEPROM Clock Toggling this bit generates a serial EEPROM clock 23:0 Reserved Table 5-6 : Serial EEPROM and Initialization Control (CNTRL) TPMC321 User Manual Issue 1.0.0 Page 13 of 33... -
Page 14: General Purpose I/O Control (Gpioc)
GPIO0 represents DONE state. Hence the direction configuration is not implemented (input only). Reserved Table 5-7 : General Purpose I/O Control (GPIOC) The GPIO functionality has been implemented for backward-compatibility reason. TPMC321 User Manual Issue 1.0.0 Page 14 of 33... -
Page 15: Configuration Space Revision Register (Crevreg)
0xFFFF 0xFFFF 0xFFFF 0xFFFF 0xFFFF 0xFFFF 0xFFFF 0xF0 0xFFFF 0xFFFF 0xFFFF 0xFFFF 0xFFFF 0xFFFF 0xFFFF 0xFFFF Table 5-9: Serial EEPROM Content Subsystem-ID Value (Offset 0x0C): TPMC321-10R: 0x000A TPMC321-11R: 0x000B TPMC321-12R: 0x000C TPMC321 User Manual Issue 1.0.0 Page 15 of 33... -
Page 16: Functional Register Space
Positive Edge Interrupt Enable Register (PIER1) 0x28 Negative Edge Interrupt Enable Register (NIER0) 0x2C Negative Edge Interrupt Enable Register (NIER1) 0x30 - 0x7B 0xFC Functional Register Space Revision Register (FREVREG) Table 5-10 : Functional Register Space TPMC321 User Manual Issue 1.0.0 Page 16 of 33... -
Page 17: Register Description
OUT_REG_BIT_18 OUT_REG_BIT_17 OUT_REG_BIT_16 Output Port bit 31:0 Data OUT_REG_BIT_15 OUT_REG_BIT_14 OUT_REG_BIT_13 OUT_REG_BIT_12 OUT_REG_BIT_11 OUT_REG_BIT_10 OUT_REG_BIT_9 OUT_REG_BIT_8 OUT_REG_BIT_7 OUT_REG_BIT_6 OUT_REG_BIT_5 OUT_REG_BIT_4 OUT_REG_BIT_3 OUT_REG_BIT_2 OUT_REG_BIT_1 OUT_REG_BIT_0 Table 5-11 : Output Register 0 (OUT_REG0) TPMC321 User Manual Issue 1.0.0 Page 17 of 33... -
Page 18: Output Register 1 (Out_Reg1)
5.5.2.2 Output Register 1 (OUT_REG1) Please note the “Output Line Switching”-chapter. For the TPMC321-11R and -12R variants this register is read- and writeable, but the outputs are unused. Reset Symbol Description Access Value OUT_REG_BIT_63 OUT_REG_BIT_62 OUT_REG_BIT_61 OUT_REG_BIT_60 OUT_REG_BIT_59 OUT_REG_BIT_58 OUT_REG_BIT_57... -
Page 19: Input Register 0 (In_Reg0)
IN_REG_BIT_18 IN_REG_BIT_17 IN_REG_BIT_16 Input Port bit 31:0 Data IN_REG_BIT_15 IN_REG_BIT_14 IN_REG_BIT_13 IN_REG_BIT_12 IN_REG_BIT_11 IN_REG_BIT_10 IN_REG_BIT_9 IN_REG_BIT_8 IN_REG_BIT_7 IN_REG_BIT_6 IN_REG_BIT_5 IN_REG_BIT_4 IN_REG_BIT_3 IN_REG_BIT_2 IN_REG_BIT_1 IN_REG_BIT_0 Table 5-13 : Input Register 0 (IN_REG0) TPMC321 User Manual Issue 1.0.0 Page 19 of 33... -
Page 20: Input Register 1 (In_Reg1)
5.5.2.4 Input Register 1 (IN_REG1) Read directly from the I/O lines 63 to 32. For the TPMC321-11R and -12R variants this register reads 0. Reset Symbol Description Access Value IN_REG_BIT_63 IN_REG_BIT_62 IN_REG_BIT_61 IN_REG_BIT_60 IN_REG_BIT_59 IN_REG_BIT_58 IN_REG_BIT_57 IN_REG_BIT_56 IN_REG_BIT_55 IN_REG_BIT_54 IN_REG_BIT_53... -
Page 21: Output Enable Register 0 (Oe_Reg0)
0: disables the output buffer OE_REG_BIT_15 1: enables the output buffer OE_REG_BIT_14 OE_REG_BIT_13 OE_REG_BIT_12 OE_REG_BIT_11 OE_REG_BIT_10 OE_REG_BIT_9 OE_REG_BIT_8 OE_REG_BIT_7 OE_REG_BIT_6 OE_REG_BIT_5 OE_REG_BIT_4 OE_REG_BIT_3 OE_REG_BIT_2 OE_REG_BIT_1 OE_REG_BIT_0 Table 5-15: Output Enable Register 0 (OE_REG0) TPMC321 User Manual Issue 1.0.0 Page 21 of 33... -
Page 22: Output Enable Register 1 (Oe_Reg1)
5.5.2.6 Output Enable Register 1 (OE_REG1) For the TPMC321-11R and -12R variants this register is read- and writeable, but the outputs are unused. Reset Symbol Description Access Value OE_REG_BIT_63 OE_REG_BIT_62 OE_REG_BIT_61 OE_REG_BIT_60 OE_REG_BIT_59 OE_REG_BIT_58 OE_REG_BIT_57 OE_REG_BIT_56 OE_REG_BIT_55 OE_REG_BIT_54 OE_REG_BIT_53 OE_REG_BIT_52... -
Page 23: Interrupt Status Register 0 (Isr0)
Interrupts are acknowledged by writing ‘1’ to the INT_14 corresponding bit. INT_13 INT_12 INT_11 INT_10 INT_9 INT_8 INT_7 INT_6 INT_5 INT_4 INT_3 INT_2 INT_1 INT_0 Table 5-17: Interrupt Status Register 0 (ISR0) TPMC321 User Manual Issue 1.0.0 Page 23 of 33... -
Page 24: Interrupt Status Register 1 (Isr1)
The Interrupt Status Register signals the lines on which an interrupt event occurred. All interrupt sources are mapped to the local interrupt LINT1#. The local interrupt LINT1# is used in active low-level sensitive mode. For the TPMC321-11R and -12R variants this register reads 0. Reset... -
Page 25: Positive Edge Interrupt Enable Register 0 (Pier0)
0 = disabled PIE_15 1 = enabled PIE_14 PIE_13 PIE_12 PIE_11 PIE_10 PIE_9 PIE_8 PIE_7 PIE_6 PIE_5 PIE_4 PIE_3 PIE_2 PIE_1 PIE_0 Table 5-19: Positive Edge Interrupt Enable Register 0 (PIER0) TPMC321 User Manual Issue 1.0.0 Page 25 of 33... -
Page 26: Positive Edge Interrupt Enable Register 1 (Pier1)
5.5.2.10 Positive Edge Interrupt Enable Register 1 (PIER1) For the TPMC321-11R and -12R variants this register is read- and writeable, but the interrupts are unused. Reset Symbol Description Access Value PIE_63 PIE_62 PIE_61 PIE_60 PIE_59 PIE_58 PIE_57 PIE_56 PIE_55 PIE_54... -
Page 27: Negative Edge Interrupt Enable Register 0 (Nier0)
0 = disabled NIE_15 1 = enabled NIE_14 NIE_13 NIE_12 NIE_11 NIE_10 NIE_9 NIE_8 NIE_7 NIE_6 NIE_5 NIE_4 NIE_3 NIE_2 NIE_1 NIE_0 Table 5-21: Negative Edge Interrupt Enable Register 0 (NIER0) TPMC321 User Manual Issue 1.0.0 Page 27 of 33... -
Page 28: Negative Edge Interrupt Enable Register 1 (Nier1)
5.5.2.12 Negative Edge Interrupt Enable Register 1 (NIER1) For the TPMC321-11R and -12R variants this register is read- and writeable, but the interrupts are unused. Reset Symbol Description Access Value NIE_63 NIE_62 NIE_61 NIE_60 NIE_59 NIE_58 NIE_57 NIE_56 NIE_55 NIE_54... -
Page 29: Functional Space Revision Register (Frevreg)
5.5.2.13 Functional Space Revision Register (FREVREG) Reset Symbol Description Access Value 31:0 FREVREG Firmware Version Register for Functional Space Table 5-23: Revision Register (FREVREG) *) Depends on Firmware Version TPMC321 User Manual Issue 1.0.0 Page 29 of 33... -
Page 30: Functional Description
Figure 6-1 : TTL I/O Interface 6.1.1 Output Line Switching Please note that the length (and consequently the capacitance) of a flat cable, connected to the TPMC321 module, should be kept as short as possible to prevent large cross talk. -
Page 31: Ttl Buffer Pull Up Voltage
If necessary, some termination resistor must be removed. The actual data transmission rate depends on factors like connection, cable length, FPGA design etc. TPMC321 User Manual Issue 1.0.0 Page 31 of 33... -
Page 32: Optional P14 Ground Connections
Figure 6-5 : Optional GND connection solder bridges on PCB bottom side (pads marked in red) Caution: Never make simultaneous connections on both jumper positions of an I/O line. Serious damage of the module is possible. TPMC321 User Manual Issue 1.0.0 Page 32 of 33... -
Page 33: Pin Assignment - I/O Connector
IO_62 IO_31- IO_31- IO_31 IO_15+ IO_15+ 64 *) IO_63 IO_31+ IO_31+ *) These pins allow an alternative ground connection, see “Optional P14 Ground Connections” Table 7-1 : P14 Back I/O Connector TPMC321 User Manual Issue 1.0.0 Page 33 of 33...