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Tews Technologies TXMC638 User Manual

Reconfigurable fpga with 24 x 16 bit analog input
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The Embedded I/O Company
TXMC638
Reconfigurable FPGA with 24 x 16 Bit Analog Input
Version 1.0
User Manual
Issue 1.0.2
October 2017
TEWS TECHNOLOGIES GmbH
Am Bahnhof 7
25469 Halstenbek, Germany
Phone: +49 (0) 4101 4058 0
Fax: +49 (0) 4101 4058 19
e-mail:
info@tews.com
www.tews.com

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  • Page 1 TXMC638 Reconfigurable FPGA with 24 x 16 Bit Analog Input Version 1.0 User Manual Issue 1.0.2 October 2017 TEWS TECHNOLOGIES GmbH Am Bahnhof 7 25469 Halstenbek, Germany Phone: +49 (0) 4101 4058 0 Fax: +49 (0) 4101 4058 19 e-mail: info@tews.com...
  • Page 2 TXMC638-11R in this document at any time without notice. 24 x Analog In and 64 direct FPGA Back I/O TEWS TECHNOLOGIES GmbH is not liable for any Lines, damage arising out of the application or use of the XC7K325T-2 FBG676 Kintex-7 FPGA, 1GB device described herein.
  • Page 3 Additions to the technical specifiction and correction of the MGT Connections Table. 1.0.1 November 2016 User FPGA Configuration Flow Charts enhanced. 1.0.2 Insert the missing Flow Charts in Chapter 7.4.2 to 7.4.8. October 2017 TXMC638 User Manual Issue 1.0.2 Page 3 of 86...

  • Page 4: Table Of Contents

    ISP Configuration Register - 0xE4..................19 5.2.7 ISP Command Register - 0xE8....................20 5.2.8 ISP Status Register - 0xEC ....................20 5.2.9 TXMC638 Serial Number - 0xF8 ....................21 5.2.10 BCC - FPGA Code Version - 0xFC..................21 INTERRUPTS......................22 Interrupt Sources ..........................22 6.1.1 User FPGA (Kintex-7)......................22 6.1.2...
  • Page 5 P16 Back I/O Connector .......................69 10.4.1 Connector Type ........................69 10.4.2 Pin Assignment ........................69 10.5 X4 FPGA JTAG Header .........................70 10.5.1 Connector Type ........................70 10.5.2 Pin Assignment ........................70 11 APPENDIX A....................... 71 TXMC638 User Manual Issue 1.0.2 Page 5 of 86...
  • Page 6 FIGURE 7-14: CONFIGURATION FPGA SLAVE ACCESS ................56 FIGURE 7-15: TXMC638 WITH HEATSINK ....................58 FIGURE 9-1 : FPGA JTAG CONNECTOR X4 ....................63 FIGURE 10-1: PIN ASSIGNMENT P14 BACK I/O CONNECTOR TXMC638 ..........68 FIGURE 10-2: PIN ASSIGNMENT P16 BACK I/O CONNECTOR TXMC638 ..........69 TXMC638 User Manual Issue 1.0.2...
  • Page 7 TABLE 5-8 : ISP STATUS REGISTER ......................20 TABLE 5-9 : TXMC638 SERIAL NUMBER .....................21 TABLE 5-10: BCC - FPGA CODE VERSION....................21 TABLE 7-1 : TXMC638 FPGA FEATURE OVERVIEW ..................24 TABLE 7-2 : FPGA BANK USAGE.........................24 TABLE 7-3 : MGT CONNECTIONS .......................25 TABLE 7-4 : MULTI GIGABIT TRANSCEIVER REFERENCE CLOCKS ............26...

  • Page 8: Product Description

    JTAG header for read back and real-time debugging of the FPGA design by using the Xilinx Vivado Logic Analyzer. User applications for the TXMC638 with Kintex-7 FPGA can be developed using the Xilinx design software Vivado Design Suite. A license for the Vivado Design Suite design tool is required.

  • Page 9: Technical Specification

    PCI Express to PCI Bridge User configurable FPGA TXMC638-10R: XC7K160T-2FBG676I (Xilinx) TXMC638-11R: XC7K325T-2FBG676I (Xilinx) TXMC638-12R: XC7K410T-2FBG676I (Xilinx) N25Q128A (Micron) 128 Mbit (contains TXMC638 FPGA Example) or SPI-Flash compatible; +3.3V supply voltage DDR3 RAM 2 x MT41K256M16HA-125 (Micron) 256 Meg x 32 Bit...

  • Page 10: Table 2-1 : Technical Specification

    If FIT rates are not available, MIL-HDBK-217F and MIL-HDBK-217F Notice 2 formulas are used for FIT rate calculation. Humidity 5 – 95 % non-condensing Weight TXMC638-xxR: 133g Table 2-1 : Technical Specification TXMC638 User Manual Issue 1.0.2 Page 10 of 86...

  • Page 11: Handling And Operation Instruction

    3 Handling and Operation Instruction ESD Protection The TXMC638 is sensitive to static electricity. Packing, unpacking and all other handling of the TXMC638 has to be done in an ESD/EOS protected Area. Thermal Considerations Forced air cooling is recommended during operation. Without forced air cooling, damage to the device can occur.

  • Page 12: Pci Device Topology

    4 PCI Device Topology The TXMC638 consists of two FPGAs. Both FPGA are designed as a PCIe / PCI endpoint devices. One FPGA is the User FPGA (Kintex-7) which could be programmed with user defined FPGA code. The second FPGA takes control of on-board hardware functions of TXMC638 and also the configuration control of the User FPGA.

  • Page 13: User Fpga (Kintex-7)

    Table 4-2 : PCI Configuration Registers 4.2.2 PCI BAR Overview Port Size Endian Space Prefetch Width Description (Byte) Mode (Bit) Little Local Configuration Register Space Little In-System Programming Data Space Table 4-3 : PCI BAR Overview TXMC638 User Manual Issue 1.0.2 Page 13 of 86...

  • Page 14: Local Configuration Register Space

    ISP Configuration Register (SPI) 0xE8 ISP Command Register (SPI) 0xEC ISP Status Register (SPI) 0xF0 Reserved 0xF4 Reserved 0xF8 TXMC638 Serial Number 0xFC BCC Code Version Table 4-4 : Local Configuration Register Space TXMC638 User Manual Issue 1.0.2 Page 14 of 86...

  • Page 15: In-System Programming Data Space

    Control and status register for ISP are located in the Local Configuration Register Space. The data register for direct FPGA ISP is also located in the Local Configuration Register Space. TXMC638 User Manual Issue 1.0.2 Page 15 of 86...

  • Page 16: Register Description

    When set, the PCI INTA# interrupt is asserted. The Interrupt is cleared by writing a ‘1’. ISP_DAT_IS 0: Interrupt not active or disabled 1: Interrupt active and enabled Table 5-2 : Interrupt Status Register TXMC638 User Manual Issue 1.0.2 Page 16 of 86...

  • Page 17: User Fpga Configuration Control/Status Register - 0Xd0

    1: Slave SelectMap (Parallel) FP_CFG_MD After power-up the User FPGA automatically configures from the on-board SPI Flash in ‘Master Serial / SPI’ mode. Table 5-3 : User FPGA Configuration Control/Status Register TXMC638 User Manual Issue 1.0.2 Page 17 of 86...

  • Page 18: User Fpga Configuration Data Register - 0Xd4

    Table 5-4 : User FPGA Configuration Data Register The User FPGA Configuration Data Register is used to write data within the User FPGA Slave Select Map Configuration directly to the User FPGA. TXMC638 User Manual Issue 1.0.2 Page 18 of 86...

  • Page 19: Isp Control Register - 0Xe0

    0x00 SPI Flash Instruction Code 0x00 Supported Instructions: 0x02 – Page Program ISP_SPI_INS 0x20 – Sector Erase 0xC7 – Chip Erase 0x03 – Read Data Table 5-6 : ISP Configuration Register TXMC638 User Manual Issue 1.0.2 Page 19 of 86...

  • Page 20: Isp Command Register - 0Xe8

    (in read mode). Capable of generating an event based interrupt. 0: No ISP SPI Data Transfer in Progress 1: ISP SPI Data Transfer in Progress Table 5-8 : ISP Status Register TXMC638 User Manual Issue 1.0.2 Page 20 of 86...

  • Page 21: Txmc638 Serial Number - 0Xf8

    5.2.9 TXMC638 Serial Number - 0xF8 Reset Symbol Description Access Value The value is the unique serial number of each 31:0 S_NUMBER TXMC638 module Table 5-9 : TXMC638 Serial Number Example: 0x0091_981A => SNo.: 9541658 The serial number can also be read via an I2C interface from User FPGA (KIntex-7).

  • Page 22: Interrupts

    The interrupt handling depends on the user application and is not part of this target specification. 6.2.2 Board Configuration Controller (BCC - FPGA) Both Interrupts of the BCC FPGA must be cleared via writing access to the corresponding Interrupt Status Flag in the Interrupt Status Register. TXMC638 User Manual Issue 1.0.2 Page 22 of 86...

  • Page 23: Functional Description

    - Select Map Bank 115, 116 - SPI Conf. - I2C PCI-Express & P16 MGTs SPI-Flash (FPGA Conf. Data) PCIe Switch P16 Back I/O 4 x MGT Figure 7-1 : FPGA Block Diagram TXMC638 User Manual Issue 1.0.2 Page 23 of 86...

  • Page 24: User Fpga Highlights

    406,720 63.550 1540 1590 28,620 Table 7-1 : TXMC638 FPGA Feature Overview PCI Express Highlights: Compliant to the PCI Express Base Specification 2.1 with Endpoint and Root Port capability. Supports Gen1 (2.5 Gb/s) and Gen2 (5 Gb/s) XADC Highlights: XADC (Analog-to-Digital Converter) On-chip temperature (±4°C max error) and power supply (±1% max error) sensors...

  • Page 25: User Fpga Gigabit Transceiver (Mgt)

    User FPGA Gigabit Transceiver (MGT) The TXMC638 provides four MGT as Kintex-7 PCI Express Endpoint Block and four MGT for high speed XMC P16 interface. PCIe X4 Interface PCIe X4 Interface Ref. Clock PCIe Clock 100 MHz 156.25 MHz Kintex-7...

  • Page 26: Table 7-4 : Multi Gigabit Transceiver Reference Clocks

    K6 / K5 not connected MGTREFCLK0_116 REFCLKO2 D6 / D5 100 MHz PI7C9X2G312GP PCIe Switch MGTREFCLK1_116 not used F6 / F5 not connected Table 7-4 : Multi Gigabit Transceiver Reference Clocks TXMC638 User Manual Issue 1.0.2 Page 26 of 86...

  • Page 27: User Fpga Configuration

    PCIe Interface via BCC FPGA Slave Select Map Interface Configuration The change of the configuration mode is done with a configuration register of the BCC FPGA. At Power-up, the TXMC638 User FPGA (Kintex-7) always configures via x4 SPI Interface by “Master Serial / SPI” mode.

  • Page 28: Manually User Fpga Spi Flash Reconfiguration

    If the PCIe interface of the User FPGA PCIe Endpoint does not change. Device ID, Vendor ID, Class Code and PCI bars do not change, the PCI header could be saved before the FPGA Re-configuration and written back to configuration space after the Re-configuration. TXMC638 User Manual Issue 1.0.2 Page 28 of 86...

  • Page 29: Slave Select Map Configuration

    After Re-configuration was successful the User FPGA Configuration Mode Set ISP_ENA = 0 and the ISP Mode could be disabled. Also the link between the PCIe Switch Set K7_LINK_ENA = 1 and the Kintex-7 must be enabled. TXMC638 User Manual Issue 1.0.2 Page 29 of 86...
  • Page 30 This is also a binary configuration data file but without header information. For configure the Kintex-7 FPGA of the TXMC638 both files could be used. Both binary configuration data file have addition data to the actual configuration data.

  • Page 31: Configuration Via Jtag

    7.4.4 Configuration via JTAG The TXMC638 provides two JTAG chains which are accessible by one of the following connector options: User JTAG Chain JST XRS Debug Connector TEWS Factory configuration Chain XMC Connector P15 The User JTAG Chain is accessible from the JST XRS Debug Connector.

  • Page 32: Programming User Fpga Spi Configuration Flash

    The Programming Instruction always starts at address 0x00 to write data from the ISP Programming Data Space to the SPI flash. If not all configuration data bytes are written, the User FPGA is not configured correctly. TXMC638 User Manual Issue 1.0.2 Page 32 of 86...

  • Page 33: Erasing User Fpga Spi Configuration Flash

    After completion of the erasing process, the ISP Mode bit should be Set FP_CFG_MD = 0 cleared to set configuration path to User FPGA or a User FPGA SPI Set ISP_ENA = 0 Configuration Flash programming process could be done. TXMC638 User Manual Issue 1.0.2 Page 33 of 86...

  • Page 34: Sector Erasing User Fpga Spi Configuration Flash

    After completion of the erasing process, the ISP Mode bit should be Set FP_CFG_MD = 0 cleared to set configuration path to User FPGA or a User FPGA SPI Set ISP_ENA = 0 Configuration Flash programming process could be done. TXMC638 User Manual Issue 1.0.2 Page 34 of 86...

  • Page 35: Reading User Fpga Spi Configuration Flash

    User FPGA. Set ISP_ENA = 0 Board Configuration Controller (BCC – FPGA) The Board Configuration FPGA is factory configured, and handles the basic board setup and User FPGA (Kintex-7) Configuration. TXMC638 User Manual Issue 1.0.2 Page 35 of 86...

  • Page 36: Clocking

    Clocking 7.6.1 FPGA Clock Sources As a central clock generator of TXMC638 the Si5338 clock generator is used. This provides all necessary clocks for the User FPGA and the Configuration FPGA. The following figure depicts an abstract User FPGA clock flow.

  • Page 37: Table 7-5 : Available Fpga Clocks

    The following table lists the available clock sources on the TXMC638: FPGA Clock-Pin Name FPGA Pin Source Description Number MGTREFCLK0_115 H6 / H5 SI5338 low-jitter clock 156.25 MHz differential generator MGT Reference clock MGTREFCLK0_116 D6 / D5 PCIe Switch 100 MHz differential...

  • Page 38: Si514 Free Programming Clock Source

    MHz with programming resolution of 0.026 parts per billion. The Si514 on TXMC638 is factory configured to 156 MHz default frequency. The Si514 is connected via I2C interface to User FPGA (Kintex-7). As usual for the I2C interface the two pins must be realized as open drain buffer.

  • Page 39: Back I/O Interface

    Back I/O Interface P14 Back I/O Pins of the TXMC638 are direct routed to the User FPGA (Kintex-7). The I/O functions of these FPGA pins are directly dependent on the configuration of the FPGA. The Kintex-7 VCCO voltage is set to 2.5V, so only the 2.5V I/O standards LVCMOS25, LVTTL25 and LVDS_25 are possible for using on TXMC638 back I/O interface.

  • Page 40: Table 7-7 : Digital Back I/O Interface

    BACK_IO28+ IN/OUT LVDS_25 BACK_IO28- IN/OUT LVDS_25 BACK_IO29+ IN/OUT LVDS_25 BACK_IO29- IN/OUT LVDS_25 BACK_IO30+ IN/OUT LVDS_25 BACK_IO30- IN/OUT LVDS_25 BACK_IO31+ IN/OUT LVDS_25 BACK_IO31- IN/OUT LVDS_25 Table 7-7 : Digital Back I/O Interface TXMC638 User Manual Issue 1.0.2 Page 40 of 86...

  • Page 41: Memory

    Memory The TXMC638 is equipped with a 1 GB, 32 bit wide DDR3 SDRAM and a 128-Mbit non-volatile SPI-Flash. The SPI-Flash can also be used as configuration memory. 7.8.1 DDR3 SDRAM The TXMC638 provides two MT41… (96-ball) DDR3 memory devices. The memory is accessible through a Memory Interface Controller Block IP in bank 32, 33 and 34 of the User FPGA.

  • Page 42: Table 7-8 : Ddr3 Sdram Interface

    DQ14 DQ31 DQ15 CK_p AC13 CK_n AD13 DQS_0_p AE18 LDQS DQS_0_n AF18 LDQS# DQS_1_p UDQS DQS_1_n UDQS# DQS_2_p LDQS DQS_2_n LDQS# DQS_3_p UDQS DQS_3_n UDQS# Table 7-8 : DDR3 SDRAM Interface TXMC638 User Manual Issue 1.0.2 Page 42 of 86...
  • Page 43 Both DDR3 Memory Devices 01 & 02 For details regarding the DDR3 SDRAM interface, please refer to XILINX Memory Interface Generator Documentation. Xilinx UG586: Zynq-7000 AP SoC and 7 Series Devices Memory Interface Solutions v4.0. TXMC638 User Manual Issue 1.0.2 Page 43 of 86...

  • Page 44: Spi-Flash

    7.8.2 SPI-Flash The TXMC638 provides a Micron N25Q128A 128-Mbit serial Flash memory. This Flash is used as FPGA configuration source (default configuration source). After configuration, it is always accessible from the FPGA, so it also can be used for code or user data storage.

  • Page 45: Adc Calibration Data Values

    0x05D ADC Channel 24 Offset Low Byte corr 0x05E ADC Channel 24 Gain High Byte corr 0x05F ADC Channel 24 Gain Low Byte corr Table 7-11: ADC Calibration Data Values TXMC638 User Manual Issue 1.0.2 Page 45 of 86...

  • Page 46: Adc Data Correction Formula

    7.8.3.3 ADC Data Correction Formula Please use the total 16 bit data register value for the ADC correction formula. The basic formula for correcting any ADC reading for the TXMC638 (bipolar input voltage range) is: Gain Offset corr corr Value = Reading 131072 Value is the corrected result.

  • Page 47: Serial Adc Interface

    Serial ADC Interface 7.9.1 Overview The 24 analog inputs of the TXMC638 are realized with 12 LTC2323-16 ADC devices. Each of these SAR- ADCs has two ADC channels. Thus, a total of 24 ADC channels are available on the TXMC638.

  • Page 48: Adc Digital Output Coding

    VIN- and VIN+. An Example: The TXMC638 voltage range is rounded ±2.5 V, so the allowed (single ended, ground related) voltage on each ADC input pin is ±2.5 V. When we examine the two largest differential voltages, we get...

  • Page 49: User Fpga Pinning

    2.5V Differential Data from ADC Channel 5 SDO1_02- 2.5V SDO2_02+ 2.5V AD21 Differential Data from ADC Channel 6 SDO2_02- 2.5V AE21 Convert Signal for ADC CNV_N_02 2.5V Channel 5 and 6 TXMC638 User Manual Issue 1.0.2 Page 49 of 86...
  • Page 50 2.5V SDO1_05+ 2.5V Differential Data from ADC Channel 11 SDO1_05- 2.5V SDO2_05+ 2.5V Differential Data from ADC Channel 12 SDO2_05- 2.5V Convert Signal for ADC CNV_N_05 2.5V Channel 11 and 12 TXMC638 User Manual Issue 1.0.2 Page 50 of 86...
  • Page 51 Differential Data from ADC Channel 17 SDO1_08- 2.5V AC22 SDO2_08+ 2.5V AD23 Differential Data from ADC Channel 18 SDO2_08- 2.5V AD24 Convert Signal for ADC CNV_N_08 2.5V AC26 Channel 17 and 18 TXMC638 User Manual Issue 1.0.2 Page 51 of 86...

  • Page 52: Table 7-14: Adc Interface Connections

    Table 7-14: ADC Interface Connections For using the clocked serial interface between the User FPGA (Kintex-7) and one of the twelve LTC2323-16 ADC devices please use the LTC2323-16 data sheet which describes the communication process. TXMC638 User Manual Issue 1.0.2 Page 52 of 86...

  • Page 53: Programming Hints Ltc2323-16

    A detailed description of the LTC2323-16 interface and the LTC2323-16 function please use the data sheet which describes the whole communication process and all special characteristics of the ADC. TXMC638 User Manual Issue 1.0.2 Page 53 of 86...

  • Page 54: Ac Coupled Differential Inputs

    7.10 AC coupled differential Inputs The TXMC638 provides three 100 Ohm terminated, ac-coupled, differential Inputs. These inputs could be used as GPIO inputs or trigger input for ADC conversion. Despite the ac-coupling, also dc-signals are supported after an initial edge.

  • Page 55: Serial Number Allocation

    Example: 0x0091_981A => SNo.: 9541658 7.11.1 Device Addressing and Operation The TXMC638 Configuration FPGA uses a standard 7 bit Slave Address. The eighth bit of the slave address is the Read/write operation select bit. 0 1 1 0 1 0 1 R/W...

  • Page 56: Read Operation

    Figure 7-13: Configuration FPGA Output Acknowledge 7.11.2 Read Operation The TXMC638 Configuration FPGA provides only one 32 bit register which could be read from User FPGA via a I2C Interface. The read operation starts with a I2C start condition followed by a 7 bit slave address. The read/write bit in the device address byte is set to one.

  • Page 57: On-Board Indicators

    7.12 On-Board Indicators The TXMC638 provides a couple of board-status LEDs as shown below. These include Power-Good and FPGA configuration status indications as well as two general purpose LEDs. Color State Description On-Board Power Supplies are not ok Power Good...

  • Page 58: Thermal Management

    I/O circuitry and the applied cooling method. A simple system air cooling is not sufficient heavy utilization of FPGA. Since the heat sink of the TXMC638 always mounted between PCB of the Carrier and PCB of the TXMC, targeted ventilation is highly recommended.

  • Page 59: Design Help

    8 Design Help Board Reference Design User applications for the TXMC638 may be developed by using the TXMC638 FPGA Board Reference Design. TEWS offers this Board Reference Design as a well-documented example basic example. It includes an .xdc constrain file with all necessary pin assignments and basic timing constraints. The example design covers the main functionalities of the TXMC638.

  • Page 60: Installation

    Maximum VIN = ±5.0V Maximum VIN = ±5.0V The TXMC638 has differential analog inputs. When talking about the input voltage range of a differential input, one has to differentiate between the differential input voltage between the two pins, and the input voltage relative to ground for each pin.
  • Page 61 +5V to -5V, but contains no information about the allowed voltage relative to ground for each input pin. If e.g. VIN+ = 98V and VIN- = 102V, the differential input voltage would be -4V. But the input common mode voltage is 100V, truly damaging the TXMC638. Example analog Input Level:...

  • Page 62: Front I/O - Ac Coupled Differential Inputs

    VIN = ±200mV up to ±3.6V 9.1.3 Back I/O Interface P14 Back I/O Pins of the TXMC638 are direct routed to the User FPGA (Kintex-7). The I/O functions of these FPGA pins are directly dependent on the configuration of the FPGA.

  • Page 63: Fpga Jtag Connector

    FPGA JTAG chain, e.g. for FPGA read back and real-time debugging of the User FPGA design (using Xilinx Vivado Logic Analyzer). The Debug Connector provides the User FPGA (Kintex-7) JTAG interface and two TXMC638 status signals. The JTAG interface consists of the signals TDI, TDO, TMS, TCK, uses 3.3V I/O voltage, and can run with up to 10 MHz.

  • Page 64: Pin Assignment - I/O Connector

    10 Pin Assignment – I/O Connector 10.1 Overview TXMC638 User Manual Issue 1.0.2 Page 64 of 86...

  • Page 65: X1 Front Panel I/O Connector

    ADC_IN16+ ADC_IN4- ADC_IN16- ADC_IN17+ ADC_IN5+ ADC_IN5- ADC_IN17- ADC_IN18+ ADC_IN6+ ADC_IN6- ADC_IN18- ADC_IN19+ ADC_IN7+ ADC_IN19- ADC_IN7- ADC_IN8+ ADC_IN20+ ADC_IN20- ADC_IN8- ADC_IN9+ ADC_IN21+ ADC_IN9- ADC_IN21- ADC_IN10+ ADC_IN22+ ADC_IN10- ADC_IN22- ADC_IN11+ ADC_IN23+ ADC_IN11- ADC_IN23- TXMC638 User Manual Issue 1.0.2 Page 65 of 86...

  • Page 66: Table 10-1: Pin Assignment Front Panel I/O Connector X1

    Connector View ADC_IN12+ ADC_IN24+ ADC_IN12- ADC_IN24- n.c. n.c. n.c. n.c. n.c. DIFF_IN2+ n.c. DIFF_IN2- n.c. DIFF_IN1+ n.c. DIFF_IN1- n.c. DIFF_IN0+ n.c. DIFF_IN0- Table 10-1: Pin Assignment Front Panel I/O Connector X1 TXMC638 User Manual Issue 1.0.2 Page 66 of 86...

  • Page 67: Back I/O Xmc Connector P14

    BACK_IO22+ BACK_IO6- BACK_IO22- BACK_IO7+ BACK_IO23+ BACK_IO7- BACK_IO23- BACK_IO8+ BACK_IO24+ BACK_IO8- BACK_IO24- BACK_IO9+ BACK_IO25+ BACK_IO9- BACK_IO25- BACK_IO10+ BACK_IO26+ BACK_IO10- BACK_IO26- BACK_IO11+ BACK_IO27+ BACK_IO11- BACK_IO27- BACK_IO12+ BACK_IO28+ BACK_IO12- BACK_IO28- BACK_IO13+ BACK_IO29+ BACK_IO13- BACK_IO29- TXMC638 User Manual Issue 1.0.2 Page 67 of 86...

  • Page 68: Figure 10-1: Pin Assignment P14 Back I/O Connector Txmc638

    BACK_IO14+ BACK_IO30+ BACK_IO14- BACK_IO30- BACK_IO15+ BACK_IO31+ BACK_IO15- BACK_IO31- Figure 10-1: Pin Assignment P14 Back I/O Connector TXMC638 TXMC638 User Manual Issue 1.0.2 Page 68 of 86...

  • Page 69: P16 Back I/O Connector

    Tx 3- Reserved Reserved Reserved Reserved Rx 0+ Rx 0- Rx 1+ Rx 1- Rx 2+ Rx 2- Rx 3+ Rx 3- Figure 10-2: Pin Assignment P16 Back I/O Connector TXMC638 TXMC638 User Manual Issue 1.0.2 Page 69 of 86...

  • Page 70: X4 Fpga Jtag Header

    JTAG chain. The pinout of this header matches the pinout of TEWS TA308 Cable Kit. In conjunction with this Cable Kit, the Xilinx Platform Cable USB II could be connected to the TXMC638. This allows the direct usage of Xilinx software-tools like Vivado Logic Analyzer or the Vivado Hardware Manager.
  • Page 71 Target Device : XC7K160T-FBG676-1 Design Tool : Xilinx Vivado Design Suite Design Edition 2015.3 Simulation Tool : Description : Constraint file TXMC638 FPGA/K7 Firmware Owner : TEWS TECHNOLOGIES GmbH Am Bahnhof 7 D-25469 Halstenbek Tel.: +49 / (0)4101 / 4058-0 Fax.: +49 / (0)4101 / 4058-19...
  • Page 72 #set_property PACKAGE_PIN L25 [get_ports {Si514_CLK_N}] ## ############################################################################################# ## ## Section: PCIe Switch ## ############################################################################################# ## set_property IOSTANDARD LVCMOS33 [get_ports DWN_RST_n] set_property PACKAGE_PIN K21 [get_ports DWN_RST_n] ## ############################################################################################# ## ## Section: DDR3 ## ############################################################################################# ## TXMC638 User Manual Issue 1.0.2 Page 72 of 86...
  • Page 73 IOSTANDARD SSTL135_T_DCI [get_ports {DQ[18]}] set_property PACKAGE_PIN U1 [get_ports {DQ[18]}] set_property SLEW FAST [get_ports {DQ[19]}] set_property IOSTANDARD SSTL135_T_DCI [get_ports {DQ[19]}] set_property PACKAGE_PIN V3 [get_ports {DQ[19]}] set_property SLEW FAST [get_ports {DQ[20]}] set_property IOSTANDARD SSTL135_T_DCI [get_ports {DQ[20]}] TXMC638 User Manual Issue 1.0.2 Page 73 of 86...
  • Page 74 PACKAGE_PIN V9 [get_ports {A[6]}] set_property SLEW FAST [get_ports {A[7]}] set_property IOSTANDARD SSTL135 [get_ports {A[7]}] set_property PACKAGE_PIN Y10 [get_ports {A[7]}] set_property SLEW FAST [get_ports {A[8]}] set_property IOSTANDARD SSTL135 [get_ports {A[8]}] set_property PACKAGE_PIN Y11 [get_ports {A[8]}] TXMC638 User Manual Issue 1.0.2 Page 74 of 86...
  • Page 75 PACKAGE_PIN AC12 [get_ports {ODT[0]}] # DDR3 Chip Select (CS, active-low) set_property SLEW FAST [get_ports {CS_n[0]}] set_property IOSTANDARD SSTL135 [get_ports {CS_n[0]}] set_property PACKAGE_PIN AA13 [get_ports {CS_n[0]}] # DDR3 Data Mask (DM) TXMC638 User Manual Issue 1.0.2 Page 75 of 86...
  • Page 76 SLEW FAST [get_ports {REF_CLK_P}] set_property IOSTANDARD DIFF_SSTL135 [get_ports {REF_CLK_P}] set_property PACKAGE_PIN AA10 [get_ports {REF_CLK_P}] set_property SLEW FAST [get_ports {REF_CLK_N}] set_property IOSTANDARD DIFF_SSTL135 [get_ports {REF_CLK_N}] set_property PACKAGE_PIN AB10 [get_ports {REF_CLK_N}] create_clock -period 5 [get_ports REF_CLK_P] TXMC638 User Manual Issue 1.0.2 Page 76 of 86...
  • Page 77 PACKAGE_PIN T24 [get_ports {ADC_SCK_P[1]}] set_property IOSTANDARD LVDS_25 [get_ports {ADC_SCK_N[1]}] # External Termination set_property PACKAGE_PIN T25 [get_ports {ADC_SCK_N[1]}] set_property IOSTANDARD LVDS_25 [get_ports {ADC_SCKOUT_P[1]}] set_property DIFF_TERM TRUE [get_ports {ADC_SCKOUT_P[1]}] set_property PACKAGE_PIN R21 [get_ports {ADC_SCKOUT_P[1]}] TXMC638 User Manual Issue 1.0.2 Page 77 of 86...
  • Page 78 IOSTANDARD LVDS_25 [get_ports {ADC_SDO2_P[2]}] set_property DIFF_TERM TRUE [get_ports {ADC_SDO2_P[2]}] set_property PACKAGE_PIN AD21 [get_ports {ADC_SDO2_P[2]}] set_property SLEW FAST [get_ports {ADC_SDO2_N[2]}] set_property IOSTANDARD LVDS_25 [get_ports {ADC_SDO2_N[2]}] set_property DIFF_TERM TRUE [get_ports {ADC_SDO2_N[2]}] set_property PACKAGE_PIN AE21 [get_ports {ADC_SDO2_N[2]}] TXMC638 User Manual Issue 1.0.2 Page 78 of 86...
  • Page 79 # ADC #4 set_property SLEW FAST [get_ports {ADC_CNV_n[4]}] set_property IOSTANDARD LVCMOS25 [get_ports {ADC_CNV_n[4]}] set_property PACKAGE_PIN M24 [get_ports {ADC_CNV_n[4]}] set_property IOSTANDARD LVDS_25 [get_ports {ADC_SCK_P[4]}] # External Termination set_property PACKAGE_PIN U26 [get_ports {ADC_SCK_P[4]}] TXMC638 User Manual Issue 1.0.2 Page 79 of 86...
  • Page 80 PACKAGE_PIN N26 [get_ports {ADC_SDO1_P[5]}] set_property SLEW FAST [get_ports {ADC_SDO1_N[5]}] set_property IOSTANDARD LVDS_25 [get_ports {ADC_SDO1_N[5]}] set_property DIFF_TERM TRUE [get_ports {ADC_SDO1_N[5]}] set_property PACKAGE_PIN M26 [get_ports {ADC_SDO1_N[5]}] set_property SLEW FAST [get_ports {ADC_SDO2_P[5]}] set_property IOSTANDARD LVDS_25 [get_ports {ADC_SDO2_P[5]}] TXMC638 User Manual Issue 1.0.2 Page 80 of 86...
  • Page 81 -clock adc_bclk_6 -max 2 [get_ports {ADC_SDO2_P[6]}] set_clock_groups -asynchronous -group {adc_bclk_6} -group {USER_CLKA}; set_max_delay 10 -datapath_only -from {adc_bclk_6} -to {USER_CLKA}; set_max_delay 10 -datapath_only -from {USER_CLKA} -to {adc_bclk_6}; # ADC #7 set_property SLEW FAST [get_ports {ADC_CNV_n[7]}] TXMC638 User Manual Issue 1.0.2 Page 81 of 86...
  • Page 82 IOSTANDARD LVDS_25 [get_ports {ADC_SCKOUT_N[8]}] set_property DIFF_TERM TRUE [get_ports {ADC_SCKOUT_N[8]}] set_property PACKAGE_PIN AA22 [get_ports {ADC_SCKOUT_N[8]}] set_property SLEW FAST [get_ports {ADC_SDO1_P[8]}] set_property IOSTANDARD LVDS_25 [get_ports {ADC_SDO1_P[8]}] set_property DIFF_TERM TRUE [get_ports {ADC_SDO1_P[8]}] set_property PACKAGE_PIN AB22 [get_ports {ADC_SDO1_P[8]}] TXMC638 User Manual Issue 1.0.2 Page 82 of 86...
  • Page 83 -name adc_bclk_9 -period 9.5238095238095238095238095238095 [get_ports {ADC_SCKOUT_P[9]}] set_input_delay -clock adc_bclk_9 -min 0 [get_ports {ADC_SDO1_P[9]}] set_input_delay -clock adc_bclk_9 -max 2 [get_ports {ADC_SDO1_P[9]}] set_input_delay -clock adc_bclk_9 -min 0 [get_ports {ADC_SDO2_P[9]}] set_input_delay -clock adc_bclk_9 -max 2 [get_ports {ADC_SDO2_P[9]}] TXMC638 User Manual Issue 1.0.2 Page 83 of 86...
  • Page 84 # External Termination set_property PACKAGE_PIN K26 [get_ports {ADC_SCK_N[11]}] set_property IOSTANDARD LVDS_25 [get_ports {ADC_SCKOUT_P[11]}] set_property DIFF_TERM TRUE [get_ports {ADC_SCKOUT_P[11]}] set_property PACKAGE_PIN P23 [get_ports {ADC_SCKOUT_P[11]}] set_property IOSTANDARD LVDS_25 [get_ports {ADC_SCKOUT_N[11]}] set_property DIFF_TERM TRUE [get_ports {ADC_SCKOUT_N[11]}] TXMC638 User Manual Issue 1.0.2 Page 84 of 86...
  • Page 85 # I2C Interface (inter-device communication) set_property SLEW FAST [get_ports FPGA_SDA] set_property IOSTANDARD LVCMOS33 [get_ports FPGA_SDA] set_property PACKAGE_PIN G26 [get_ports FPGA_SDA] set_property SLEW FAST [get_ports FPGA_SCL] set_property IOSTANDARD LVCMOS33 [get_ports FPGA_SCL] set_property PACKAGE_PIN F25 [get_ports FPGA_SCL] TXMC638 User Manual Issue 1.0.2 Page 85 of 86...
  • Page 86 # LEDs set_property SLEW FAST [get_ports {USER_LED[0]}] set_property IOSTANDARD LVCMOS33 [get_ports {USER_LED[0]}] set_property PACKAGE_PIN J26 [get_ports {USER_LED[0]}] set_property SLEW FAST [get_ports {USER_LED[1]}] set_property IOSTANDARD LVCMOS33 [get_ports {USER_LED[1]}] set_property PACKAGE_PIN E26 [get_ports {USER_LED[1]}] TXMC638 User Manual Issue 1.0.2 Page 86 of 86...

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