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Related Manuals for Tews Technologies TMPE627
Summary of Contents for Tews Technologies TMPE627
- Page 1 Reconfigurable FPGA with AD/DA & Digital I/O PCIe Mini Card Version 1.0 User Manual Issue 1.0.2 January 2018 TEWS TECHNOLOGIES GmbH Am Bahnhof 7 25469 Halstenbek, Germany Phone: +49 (0) 4101 4058 0 Fax: +49 (0) 4101 4058 19 e-mail: info@tews.com...
- Page 2 However TEWS TECHNOLOGIES GmbH reserves the right to change the product described in this document at any time without notice. TEWS TECHNOLOGIES GmbH is not liable for any damage arising out of the application or use of the device described herein.
- Page 3 Issue Description Date 1.0.0 Initial Issue June 2017 1.0.1 Corrected typos October 2017 1.0.2 Changed Document Tilte January 2018 Added “A Remark About Slot Supplies” TMPE627 User Manual Issue 1.0.2 Page 3 of 34...
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Page 4: Table Of Contents
I/O CONNECTORS ..................... 27 Overview ............................27 Board Connectors ......................... 28 7.2.1 System Connector (X1) ......................28 7.2.2 I/O Connector (X2) ........................29 7.2.3 JTAG Connector (X3) ......................30 APPENDIX A ....................... 31 TMPE627 User Manual Issue 1.0.2 Page 4 of 34... - Page 5 FIGURE 7-2: PRELIMINARY SYSTEM CONNECTOR PIN ASSIGNMENT ........... 28 FIGURE 7-3: I/O CONNECTOR PIN ASSIGNMENT ..................29 FIGURE 7-4: XRS CONNECTOR PIN ASSIGNMENT ..................30 FIGURE 7-5: TMPE627 CONNECTED TO A PROGRAMMER VIA TA308 ............ 30 List of Tables TABLE 2-1: TECHNICAL SPECIFICATION ....................... 7 TABLE 4-1: TMPE627 FPGA FEATURE OVERVIEW ..................
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Page 6: Product Description
The example design covers the main functionalities of the TMPE627. It implements PCIe to register mapping and basic I/O. It comes as a Xilinx Vivado Design Suite project with source code and as a ready-to-download bit stream. -
Page 7: Technical Specification
0-5 V, 0-10 V, 0-10.8V, ±5 V, ±10 V, ±10.8 V I/O Connector 30 pol. Pico-Clasp latching connector Physical Data Depends on FPGA design With TMPE627 FPGA Example Design running, DACs driving the ADCs and into a 2 kΩ load: Power Requirements +3.3 Vaux: 650 mA typical +1.5 V:... -
Page 8: Handling And Operating Instructions
Express Mini Card components height. Check carefully if your application provides enough spacing for a TMPE627. Thermal Considerations Due to its small size and high density, the TMPE627 can generate a lot of heat. Forced air cooling is recommended during operation. If forced air cooling is not possible, another equivalent cooling mechanism must be applied. -
Page 9: Functional Description
Transceivers 7A50T 8150 65200 2700 Table 4-1: TMPE627 FPGA Feature Overview The FPGA is equipped with 4 I/O banks and 4 Gigabit (GTP) Transceivers. One of the GTPs can be connected to an Endpoint Block for PCI Express. Bank Signals... -
Page 10: User Fpga Gigabit Transceiver (Gtp)
TMPE627 Artix-7 device. 4.3.1 SPI-Flash The TMPE627 provides a 128-Mbit serial Flash memory, which is used as the default FPGA configuration source. After configuration the flash is accessible from the FPGA, so it also can be used for additional code or user data storage. -
Page 11: Configuration Via Jtag
JTAG Chain. 4.3.3 Generate Artix-7 Configuration Data To use the maximum configuration speed, the TMPE627 must be configured to use the 100 MHz external master clock as CCLK. To use this configuration feature, the following configuration option must be set: set_property BITSTREAM.CONFIG.EXTMASTERCCLK_EN... -
Page 12: Digital I/O Interface
DO<13> LVCMOS33 SLOW OE<0># OUTPUT LVCMOS33 SLOW OE<1># OUTPUT LVCMOS33 SLOW OE<2># OUTPUT LVCMOS33 SLOW OE<3># OUTPUT LVCMOS33 SLOW OE<4># OUTPUT LVCMOS33 SLOW OE<5># OUTPUT LVCMOS33 SLOW OE<6># OUTPUT LVCMOS33 SLOW TMPE627 User Manual Issue 1.0.2 Page 12 of 34... -
Page 13: Ttl I/O Interface
3.5 V is required. Drive DO constant low and use OE to toggle the output. With the pull voltage set to GND, a pull-down functionality is implemented. Drive DO constant high and use OE to toggle the output. TMPE627 User Manual Issue 1.0.2 Page 13 of 34... -
Page 14: User Gpio
CMOS high level, the I/O load (leakage) current should not exceed 250 µA. User GPIO The TMPE627 has some optional general purpose I/O and debug signals connected to the FPGA. The required signaling standard is LVCMOS33. TMPE627 User Manual Issue 1.0.2... -
Page 15: Adc Interface
Signal Bank Description FF_12 3.3 V Fault flag for ADC channels 1 & 2 FF_34 3.3 V Fault flag for ADC channels 3 & 4 Table 4-12: ADC Fault Flag TMPE627 User Manual Issue 1.0.2 Page 15 of 34... -
Page 16: Adc
AGND and VIN+ is used as a standard single-ended input. However, the input signals are allowed to swing with an arbitrary relationship to each other, provided each pin remains within the common mode range and VIN+ remains over VIN-. TMPE627 User Manual Issue 1.0.2 Page 16 of 34... -
Page 17: Table 4-14: Adc Input Schemes
In most cases the VIN- connection suffices. Single-Ended without Ground Reference Differential without Ground Reference VIN+ VIN+ VIN- VIN- AGND AGND Table 4-15: ADC Input Schemes Unused ADC channels should be connected to AGND. TMPE627 User Manual Issue 1.0.2 Page 17 of 34... -
Page 18: Dac Interface
~4 kΩ. This condition is indicated by the OCx bit set to ‘1’ and the PUx set to ‘0’. The channel can be powered up again by setting the PUx bit back to ‘1’ after the overload condition is relieved. TMPE627 User Manual Issue 1.0.2 Page 18 of 34... -
Page 19: I²C-Eeprom
I²C-EEPROM The TMPE627 provides an Atmel AT24C04 4-kbit I²C memory, which is used to store the ADC and DAC correction data. Although the EEPROM is not write-protected it should be generally treated as a read-only resource for FPGA designs. Refer to “4.12.2 Correction EEPROM” for details about the stored data. The device address will be “1010000”. -
Page 20: Thermal Management
As an indication: With the example application running in a standard PC enclosure at 25°C the TMPE627 current requirement is 650 mA @ 3.3 V and 200 mA @ 1.5 V, resulting in a TMPE627 board temperature of about 50°C and an internal temperature of the Artix-7 FPGA of about 60°C. -
Page 21: Adc & Dac Correction
Calibration Value ROM. corr corr Resolution is the data converter resolution in bit (for the TMPE627 it is 16 for both AD and DA) Floating point arithmetic or scaled integer arithmetic must be used to avoid rounding errors in computing above formula. -
Page 22: Correction Eeprom
ADC Channel 4 Offset 10 V CORR 0x03E ADC Channel 4 Gain 10 V CORR 0x040 ADC Channel 1 Offset 10.24 V CORR 0x042 ADC Channel 1 Gain 10.24 V CORR TMPE627 User Manual Issue 1.0.2 Page 22 of 34... - Page 23 DAC Channel 3 Offset 10 V CORR 0x09A DAC Channel 3 Gain 10 V CORR 0x09C DAC Channel 4 Offset 10 V CORR 0x09E DAC Channel 4 Gain 10 V CORR TMPE627 User Manual Issue 1.0.2 Page 23 of 34...
- Page 24 DAC Channel 4 Offset ±10.8 V CORR 0x0DE DAC Channel 4 Gain ±10.8 V CORR 0x0E0-0x1EF Reserved 0x1F0 Vendor ID (0x1498) 0x1F2 Device ID (0xA273) 0x1F4 Subsystem Vendor ID (0x1498) 0x1F6 Subsystem ID (0xA00A) TMPE627 User Manual Issue 1.0.2 Page 24 of 34...
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Page 25: Table 4-20: Correction Value Space Address Map
The Module Serial Number is stored as EUI-64 (i.e. Sn. 1234567 = 0x0001060001234567). It can be used to support the PCIe Device Serial Number Capability Table 4-20: Correction Value Space Address Map TMPE627 User Manual Issue 1.0.2 Page 25 of 34... -
Page 26: Design Help
The example design covers the main functionalities of the TMPE627. It implements a PCIe endpoint with register mapping and basic I/O functions. It comes as a Xilinx Vivado Design Suite project with source code and as a ready-to-download bit stream. -
Page 27: O Connectors
7 I/O Connectors This chapter provides information about user accessible on-board connectors Overview System Connector I/O Connector JTAG Connector Figure 7-1: I/O Connector Overview TMPE627 User Manual Issue 1.0.2 Page 27 of 34... -
Page 28: Board Connectors
+3.3 Vaux PERST# UIM_IC_DP W_DISABLE1# UIM_IC_DM Mechanical Key Mechanical Key UIM_SPU REF_CLK+ UIM_RESET REF_CLK- UIM_CLK UIM_DATA CLKREQ# UIM_PWR COEX2 +1.5 V COEX1 WAKE# +3.3 Vaux Figure 7-2: Preliminary System Connector Pin Assignment TMPE627 User Manual Issue 1.0.2 Page 28 of 34... -
Page 29: I/O Connector (X2)
Molex Pico-Clasp, dual row straight header, with lock Source & Order Info 501190-3017 Mating Part 501189-2010 The I/O connector will exceed the available PCI Express Mini Card components height. Check carefully if you application provides enough spacing for a TMPE627. Pin Assignment Description Description Single-En. Diff. -
Page 30: Jtag Connector (X3)
Mating Part 10XSR-36S The TMPE627 provides a JTAG connector to access the FPGA’s JTAG port. TEWS provides a “Programming Kit” (TA308) which includes a XSR cable and an adapter module that provides a Xilinx USB Programmer II compatible 2 mm shrouded header. - Page 31 PACKAGE_PIN [get_ports {DI[6]}] set_property PACKAGE_PIN [get_ports {DI[7]}] set_property PACKAGE_PIN [get_ports {DI[8]}] set_property PACKAGE_PIN [get_ports {DI[9]}] set_property PACKAGE_PIN [get_ports {DI[10]}] set_property PACKAGE_PIN [get_ports {DI[11]}] set_property PACKAGE_PIN [get_ports {DI[12]}] set_property PACKAGE_PIN [get_ports {DI[13]}] TMPE627 User Manual Issue 1.0.2 Page 31 of 34...
- Page 32 [get_ports DAC_BIN2S] set_property SLEW SLOW [get_ports DAC_CLR_n] set_property SLEW SLOW [get_ports DAC_LDAC_n] set_property SLEW SLOW [get_ports DAC_SCLK] set_property SLEW SLOW [get_ports DAC_SDIN] set_property SLEW SLOW [get_ports DAC_SYNC_n] set_property DRIVE [get_ports DAC_BIN2S] TMPE627 User Manual Issue 1.0.2 Page 32 of 34...
- Page 33 [get_ports VAUXN9] set_property PACKAGE_PIN [get_ports VAUXP9] # 100 MHz External Configuration Master Clock set_property IOSTANDARD LVCMOS33 [get_ports EMC_CLK] set_property PACKAGE_PIN [get_ports EMC_CLK] # Allow connection from non-clockable pin to clock nets TMPE627 User Manual Issue 1.0.2 Page 33 of 34...
- Page 34 [current_design] set_property CONFIG_VOLTAGE [current_design] set_property BITSTREAM.GENERAL.COMPRESS FALSE [current_design] ### Boot from external Clock set_property BITSTREAM.CONFIG.EXTMASTERCCLK_EN div-1 [current_design] ### SPI x4 Settings set_property BITSTREAM.CONFIG.SPI_FALL_EDGE [current_design] set_property CONFIG_MODE SPIx4 [current_design] set_property BITSTREAM.CONFIG.SPI_BUSWIDTH [current_design] TMPE627 User Manual Issue 1.0.2 Page 34 of 34...