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Related Manuals for Tews Technologies TMPE633
Summary of Contents for Tews Technologies TMPE633
- Page 1 TMPE633 Reconfigurable FPGA with Digital I/O PCIe Mini Card Version 1.0 User Manual Issue 1.0.3 April 2020 TEWS TECHNOLOGIES GmbH Am Bahnhof 7 25469 Halstenbek, Germany Phone: +49 (0) 4101 4058 0 Fax: +49 (0) 4101 4058 19 e-mail: info@tews.com...
- Page 2 13 M-LVDS I/O, Spartan-6 LX25T FPGA TEWS TECHNOLOGIES GmbH is not liable for any damage arising out of the application or use of the device described herein.
- Page 3 Initial Issue December 2015 1.0.1 Added TA308 May 2016 1.0.2 Clarification Chapters May 2016 “Product Description” and “Example Design” 1.0.3 Corrected “Mating Part” number for the I/O connector (X2) April 2020 TMPE633 User Manual Issue 1.0.3 Page 3 of 25...
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Page 4: Table Of Contents
Example Design ..........................17 FPGA MultiBoot..........................17 INSTALLATION ......................17 I/O CONNECTORS ..................... 18 Overview ............................18 Board Connectors.........................19 7.2.1 System Connector (X1) ......................19 7.2.2 I/O Connector (X2)........................20 7.2.3 JTAG Connector (X3) ......................21 APPENDIX A....................... 22 TMPE633 User Manual Issue 1.0.3 Page 4 of 25... - Page 5 FIGURE 7-2 : PRELIMINARY SYSTEM CONNECTOR PIN ASSIGNMENT ..........19 FIGURE 7-3 : I/O CONNECTOR PIN ASSIGNMENT..................20 FIGURE 7-4 : XRS CONNECTOR PIN ASSIGNMENT ..................21 FIGURE 7-5 : TMPE633 CONNECTED TO A PROGRAMMER VIA TA308 ..........21 List of Tables TABLE 2-1 : TECHNICAL SPECIFICATION.....................7 TABLE 4-1 : TMPE633 FPGA FEATURE OVERVIEW..................9...
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Page 6: Product Description
The example design covers the main functionalities of the TMPE633. It implements local Bus interface to local Bridge device, register mapping and basic I/O. It comes as a Xilinx ISE project with source code and as a ready-to-download bit stream. -
Page 7: Technical Specification
PCI Express Base Specification, Revision 2.0 The TMPE633 does not support the USB interface Main On-Board Devices User configurable XC6SLX25T-2 (Xilinx) FPGA W25Q64FV (Winbond) 64 Mbit (contains TMPE633 FPGA Example) or SPI-Flash compatible I/O Interface TMPE633-10R: 26 ESD-protected 5 V-tolerant TTL lines I/O Channels... -
Page 8: Handling And Operating Instructions
Packing, unpacking and all other module handling has to be done in an ESD/EOS protected Area. Height Restrictions The I/O connector will exceed the available PCI Express Mini Card components height. Check carefully if your application provides enough spacing for a TMPE633. TMPE633 User Manual Issue 1.0.3 Page 8 of 25... -
Page 9: Functional Description
Transceivers LX25T 3.758 30.064 Table 4-1 : TMPE633 FPGA Feature Overview The FPGA is equipped with 4 I/O banks and 2 MGT (multi gigabit transceiver). One of the MGTs can be connected to an Endpoint Block for PCI Express. Bank... -
Page 10: User Fpga Gigabit Transceiver (Gtp)
TMPE633 Spartan-6 device. 4.3.1 SPI-Flash The TMPE633 provides a Winbond W25Q64 64-Mbit serial Flash memory, which is used as the default FPGA configuration source. After configuration the flash is accessible from the FPGA, so it also can be used for additional code or user data storage. The SPI-Flash is connected via Quad (x4) SPI interface to Spartan- 6 configuration interface. -
Page 11: Configuration Via Jtag
JTAG Chain. 4.3.3 Generate Spartan-6 Configuration Data To use the maximum configuration speed, the TMPE633 must be configured to use the 40 MHz external master clock as CCLK. To use this configuration feature, the following configuration option must be set: ‘Enable External Master Clock’... -
Page 12: Digital I/O Interface
IN/OUT LVCMOS33 SLOW OE<0># OUTPUT LVCMOS33 SLOW OE<1># OUTPUT LVCMOS33 SLOW OE<2># OUTPUT LVCMOS33 SLOW OE<3># OUTPUT LVCMOS33 SLOW OE<4># OUTPUT LVCMOS33 SLOW OE<5># OUTPUT LVCMOS33 SLOW OE<6># OUTPUT LVCMOS33 SLOW TMPE633 User Manual Issue 1.0.3 Page 12 of 25... -
Page 13: Ttl I/O Interface
The pull voltage can be set to 3.3 V, 5 V or GND. 5V, 3.3V or GND DIOx I/O_x XILINX FPGA MSMF05 (Protection) Figure 4-1 : TTL I/O Interface TMPE633 User Manual Issue 1.0.3 Page 13 of 25... -
Page 14: Table 4-8 : I/O Pull Options
I/O pin. To maintain a proper 5 V CMOS high level, the I/O load (leakage) current should not exceed 250 µA. TMPE633 User Manual Issue 1.0.3 Page 14 of 25... -
Page 15: Differential I/O Interface
FPGA Figure 4-2 : Differential I/O Interface Please note that each TMPE633 M-LVDS line provides its own termination. If more than four lines are connected together some termination resistors must be removed. The actual data transmission rate depends on factors like connection, cable length, FPGA design etc. -
Page 16: Thermal Management
Forced air cooling is recommended during operation. The Spartan-6 FPGA has no heatsink mounted. If additional cooling is required, the TMPE633 can be equipped with a heatsink, for example a Fischer Elektronik ICK S 14 x 14 x 6. Contact factory for this option. -
Page 17: Design Help
The example design covers the main functionalities of the TMPE633. It implements a PCIe endpoint with register mapping and basic I/O functions. It comes as a Xilinx ISE 14.7 project with source code and as a ready-to-download bit stream. A user manual is included. -
Page 18: O Connectors
7 I/O Connectors This chapter provides information about user accessible on-board connectors Overview System Connector I/O Connector JTAG Connector Figure 7-1 : I/O Connector Overview TMPE633 User Manual Issue 1.0.3 Page 18 of 25... -
Page 19: Board Connectors
PERn0 +3.3Vaux PERST# UIM_IC_DP W_DISABLE1# UIM_IC_DM Mechanical Key Mechanical Key UIM_SPU REF_CLK+ UIM_RESET REF_CLK- UIM_CLK UIM_DATA CLKREQ# UIM_PWR COEX2 +1.5V COEX1 WAKE# +3.3Vaux Figure 7-2 : Preliminary System Connector Pin Assignment TMPE633 User Manual Issue 1.0.3 Page 19 of 25... -
Page 20: I/O Connector (X2)
I/O_x signals correspond to the DIOx/OEx FPGA pins. The DIOx/OEx FPGA pins for the I/O_x signals that are not shown in the table are not connected on this build option (i.e. I/O_13 to I/O_25 are not connected for differential board variants like TMPE633-11R or TMPE633-12R). -
Page 21: Jtag Connector (X3)
Mating Part 10XSR-36S The TMPE633 provides a JTAG connector to access the FPGA’s JTAG port. TEWS provides a “Programming Kit” (TA308) which includes a XSR cable and an adapter module that provides a Xilinx USB Programmer II compatible 2 mm shrouded header. - Page 22 # ----------------------------- 3.3 V 3.3 V 3.3 V 3.3 V # Since all banks are supplied by 3.3 V, all signals get the same default # IOSTANDARD net "*" iostandard = LVCMOS33; TMPE633 User Manual Issue 1.0.3 Page 22 of 25...
- Page 23 "DIO[7]" loc = "G18"; # Bank 1 net "DIO[8]" loc = "V12"; # Bank 2 net "DIO[9]" loc = "U7"; # Bank 2 net "DIO[10]" loc = "R7"; # Bank 2 TMPE633 User Manual Issue 1.0.3 Page 23 of 25...
- Page 24 # Bank 2, CCLK net "CSO_B" loc = "V3"; # Bank 2, CSO_B net "MOSI" loc = "T13"; # Bank 2, MOSI net "MISO" loc = "R13"; # Bank 2, D0 TMPE633 User Manual Issue 1.0.3 Page 24 of 25...
- Page 25 = "A15"; # Bank 0, SMB_DAT net "LED_WWAN" loc = "E6"; # Bank 0 net "LED_WPAN" loc = "F7"; # Bank 0 net "LED_WLAN" loc = "G8"; # Bank 0 TMPE633 User Manual Issue 1.0.3 Page 25 of 25...
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