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TPMC321-11R
Tews Technologies TPMC321-11R Manuals
Manuals and User Guides for Tews Technologies TPMC321-11R. We have
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Tews Technologies TPMC321-11R manual available for free PDF download: User Manual
Tews Technologies TPMC321-11R User Manual (33 pages)
Conducion cooled 64 Digital TTL I/O / 32 Differential I/O
Brand:
Tews Technologies
| Category:
Computer Hardware
| Size: 0.66 MB
Table of Contents
Table of Contents
4
Product Description
6
Figure 1-1 : Block Diagram
6
Technical Specification
7
Table 2-1 : Technical Specification
7
Handling and Operation Instructions
8
ESD Protection
8
Terms and Definitions
9
Register Bit Access Types
9
Style Conventions
9
Pci Interface
10
PCI Identifiers
10
PCI Base Address Register Configuration
10
Configuration Register Space
10
Table 3-5 : Pci Identifiers
10
Table 3-6 : Pci Base Address Registers
10
Register Map
11
Register Description
11
Functional Register Space Descriptor (LAS0BRD)
11
Table 7-2 : Configuration Register Space
11
Table 8-1 : Functional Register Space Descriptor (Las0Brd)
11
Interrupt Control/Status (INTCSR)
12
Table 8-2 : Interrupt Control/Status (Intcsr)
12
Serial EEPROM and Initialization Control (CNTRL)
13
Table 8-3 : Serial Eeprom and Initialization Control (Cntrl)
13
General Purpose I/O Control (GPIOC)
14
Table 8-4 : General Purpose I/O Control (Gpioc)
14
Configuration Space Revision Register (CREVREG)
15
Serial EEPROM
15
Table 8-5 : Revision Register (Crevreg)
15
Table 8-19: Serial Eeprom Content
15
Functional Register Space
16
Register Map
16
Table 7-3 : Functional Register Space
16
Register Description
17
Output Register 0 (OUT_REG0)
17
Table 8-6 : Output Register 0 (Out_Reg0)
17
Output Register 1 (OUT_REG1)
18
Table 8-7 : Output Register 1 (Out_Reg1)
18
Input Register 0 (IN_REG0)
19
Table 8-8 : Input Register 0 (In_Reg0)
19
Input Register 1 (IN_REG1)
20
Table 8-9 : Input Register 1 (In_Reg1)
20
Output Enable Register 0 (OE_REG0)
21
Table 8-10: Output Enable Register 0 (Oe_Reg0)
21
Output Enable Register 1 (OE_REG1)
22
Table 8-11: Output Enable Register 1 (Oe_Reg1)
22
Interrupt Status Register 0 (ISR0)
23
Table 8-12: Interrupt Status Register 0 (Isr0)
23
Interrupt Status Register 1 (ISR1)
24
Table 8-13: Interrupt Status Register 1 (Isr1)
24
Positive Edge Interrupt Enable Register 0 (PIER0)
25
Table 8-14: Positive Edge Interrupt Enable Register 0 (Pier0)
25
Positive Edge Interrupt Enable Register 1 (PIER1)
26
Table 8-15: Positive Edge Interrupt Enable Register 1 (Pier1)
26
Negative Edge Interrupt Enable Register 0 (NIER0)
27
Table 8-16: Negative Edge Interrupt Enable Register 0 (Nier0)
27
Negative Edge Interrupt Enable Register 1 (NIER1)
28
Table 8-17: Negative Edge Interrupt Enable Register 1 (Nier1)
28
Functional Space Revision Register (FREVREG)
29
Table 8-18: Revision Register (Frevreg)
29
Functional Description
30
TTL I/O Interface
30
Output Line Switching
30
TTL Buffer Pull up Voltage
31
Differential I/O-Interface
31
Optional P14 Ground Connections
32
Figure 6-4 : Default 0Ω Bridges on Pcb Top Side (Marked in Red)
32
Pin Assignment - I/O Connector
33
P14 Back I/O Connector
33
Table 5-1 : P14 Back I/O Connector
33
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