ST STM8 User Manual

Swim communication protocol and debug module

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UM0470

User manual

STM8 SWIM communication protocol and debug module

Introduction

This manual is addressed to developers who build programming, testing or debugging tools

for the STM8 8-bit MCUs family. This document explains the debug architecture of the

STM8 core.

The STM8 8-bit MCUs debug system includes two modules:

• DM: debug module

• SWIM: single wire interface module

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Summary of Contents for ST STM8

Page 1 STM8 SWIM communication protocol and debug module Introduction This manual is addressed to developers who build programming, testing or debugging tools for the STM8 8-bit MCUs family. This document explains the debug architecture of the STM8 core. The STM8 8-bit MCUs debug system includes two modules: •...
Page 2: Table Of Contents
3.10 STM8 MCUs SWIM registers ........18 3.10.1...
Page 3 STM8 product ........37...
Page 4 CPU register memory mapping in STM8 MCUs ....... . .
Page 5 STM8 DM instruction break timing ........
Page 6: Debug System Overview
UM0470 Debug system overview The STM8 MCUs debug system interface allows a debugging or programming tool to be connected to the MCU through a single wire. This connection results in a bidirectional communication based on an open-drain line and provides a non-intrusive read/write access to RAM and peripherals during the program execution.
Page 7: Communication Layer
UM0470 Communication layer Communication layer The SWIM is a single wire interface based on asynchronous, high sink (8 mA), open-drain, bidirectional communication. While the CPU is running, the SWIM allows a non-intrusive read/write accesses to be performed on-the-fly to the RAM and peripheral registers, for debug purposes.
Page 8: Single Wire Interface Module (Swim)
ACTIVE: this mode is entered when a specific sequence is detected on the SWIM pin while it is in the OFF state. In this state, the SWIM pin is used by the host tool to control the STM8 device with three commands: SRST (system reset), ROTF (read on-the-fly) and WOTF (write on-the-fly).
Page 9: Swim Entry Sequence
UM0470 Single wire interface module (SWIM) SWIM entry sequence After a POR (power on reset), and as long as the SWIM is in OFF mode, the SWIM pin is sampled for entry sequence detection. In order to do this, the internal LSI (low speed RC - resistor/capacitor) clock is automatically turned ON after the POR and remains forced ON as long as the SWIM is in OFF mode.
Page 10: Figure 5. Swim Entry Sequence
Once the option byte loading has occurred and that the stabilization time is reached, the CPU is in phase 8: - STM8 is stalled and HSI = 16 Mhz (see STM8 datasheets for HSI clock accuracy) - SWIM clock is at HSI/2 = 8 Mhz...
Page 11: Bit Format
UM0470 Single wire interface module (SWIM) Bit format The bit format is a return-to-zero format, which allows a synchronization of every bit. Two communication speeds are available. At SWIM activation, the low speed is selected, while the high speed is selected by setting the HS bit in the SWIM_CSR register with the SWIM protocol.
Page 12: Low Speed Bit Format
Single wire interface module (SWIM) UM0470 3.3.2 Low speed bit format 1 bit is generated with twenty-two SWIM clock pulses. The bit format is: • 2 pulses at ‘0’ followed by 20 pulses at ‘1’ for ‘1’ value. • 20 pulses at ‘0’ followed by 2 pulses at ‘1’ for ‘0’ value. When the SWIM receives a data packet, it will decode: •...
Page 13: Swim Communication Protocol
UM0470 Single wire interface module (SWIM) SWIM communication protocol When in SWIM is in ACTIVE mode, the communication can be initiated either by the host or by the device. Each byte or command is preceded by a 1-bit header in order to arbitrate if both host and device initiate the communication at the same time.
Page 14: Swim Commands
Single wire interface module (SWIM) UM0470 SWIM commands The host can send a command when the line is idle or after each data byte from the device. After sending the command, the host releases the line. When the SWIM is ready to answer to the command, it initiates the transfer.
Page 15: Wotf: Write On-The-Fly
UM0470 Single wire interface module (SWIM) 3.5.3 WOTF: write on-the-fly 1 command followed by the number of bytes to be written followed by the address on three bytes. WOTF D[@] D[@+N] Parameters: The 8 bits are the number of bytes to write (from 1 to 255) @E/H/L: This is the 24-bit address to be accessed.
Page 16: Cpu Register Access
UM0470 CPU register access The CPU registers are mapped in the STM8 memory, and they can be read or written directly using the ROTF and the WOTF SWIM commands. the write operations to the CPU registers are committed only when the CPU is stalled.
Page 17: Physical Layer
UM0470 Single wire interface module (SWIM) Physical layer During the communication, the SWIM pin will be in pseudo-open drain configuration. The SWIM pin in the device is capable of sinking 8 mA when it drives the line to 0. The external pull-up on the SWIM line should be sized in a way that the maximum rise time t of the SWIM line is less than 1 sampling period of the bit (which is 100 ns +/- 4 %).
Page 18: Stm8 Mcus Swim Registers
SAFE_MASK: Mask internal RESET sources This bit can be read or written through the SWIM only. It cannot be accessed through Bit 7 the STM8 bus. It includes the watchdog reset. 0: Internal reset sources are not masked 1: Internal reset sources are masked.
Page 19: Swim Clock Control Register (Clk_Swimccr)
HSIT: High speed internal clock is trimmed This bit is read only through SWIM only. It cannot be accessed through STM8 bus. It is set when the HSIT bit is set in the core configuration register and reset by an external Bit 1 reset.
Page 20: Debug Module (Dm)
Debug module (DM) UM0470 Debug module (DM) Introduction The debug module (DM) allows the developer to perform certain debugging tasks without using an emulator. For example, the DM can interrupt the MCU to break infinite loops or to output the core context (stack) at a given point. The DM is mainly used for in-circuit debugging.
Page 21: Figure 11. Debug Module Block Diagram
UM0470 Debug module (DM) Figure 11. Debug module block diagram DocID14024 Rev 4 21/39...
Page 22: Debug
Debug module (DM) UM0470 Debug The DM registers can be read and written only through the SWIM interface. The STM8 core has no access to these registers. 4.3.1 Reset Once the SWIM is active and that the SWIM_DM bit is set in the SWIM_CSR register, a ‘data read’...
Page 23: Breakpoint Decoding Table
UM0470 Debug module (DM) Breakpoint decoding table Table 4. Decoding table for breakpoint interrupt generation DM_CR1 DM_CSR1 BREAK CONDITIONS BK1F BK2F BRW Disabled (RESET state) Data Write on @=BK1 and Data=BK2L Data Read on @=BK1 and Data=BK2L Data R/W on @=BK1 and Data=BK2L Instruction fetch BK1<=@<=BK2 Data Write on BK1<=@<=BK2 Data Read on BK1<=@<=BK2...
Page 24: Software Breakpoint Mode
This paragraph defines when the debug module stalls the CPU when using the different breakpoint sources. • The STM8 MCU instruction can be modeled in time with an op-code/operand with a FETCH, DECODE and EXECUTION phases as shown in Figure The timing information is based on these models.
Page 25: Data Breakpoint
When the specified address does not correspond to a valid instruction address, no stall is generated. Figure 15. STM8 DM instruction break timing 4.10 Step mode The STM8 CPU stall is activated before the instruction execution, in the first decode cycle of the instruction. See Figure DocID14024 Rev 4 25/39...
Page 26: Figure 16. Stm8 Dm Step Timing
Debug module (DM) UM0470 Figure 16. STM8 DM step timing Note: When the Step mode and the instruction break on the next instruction mode are both enabled, both the STF and the BKxF flags are set. When the user clears the STALL bit, the step function continues its normal operation.
Page 27: Application Notes
Stack on @<=BK1” conditions and set BK1 to the upper value where the specific data is located in the stack. If the STM8 device tries to overwrite these values (after an interrupt or a CALL), the DM will generate a break. The four possible associated conditions allow to manage another breakpoint capability at the same time.
Page 28: Dm Registers
The SWIM can read and write to these bits via the ROTF/WOTF commands. read-only (r) The SWIM can only read these bits via the ROTF command. 4.12.1 DM breakpoint register 1 extended byte (DM_BKR1E) STM8 Address: 7F90h Reset value: 1111 1111 (FFh) BK1[23:16] BK1[23:16]: Breakpoint 1 extended byte value Bits 7:0 This register is written by software to define the extended address bits of breakpoint 1.
Page 29: Dm Breakpoint Register 2 Extended Byte (Dm_Bkr2E)
UM0470 Debug module (DM) 4.12.4 DM breakpoint register 2 extended byte (DM_BKR2E) Address: 7F93h Reset value: 1111 1111 (FFh) BK2[23:16] BK2[23:16]: Breakpoint 2 extended byte value Bits 7:0 This register is written by software to define the extended 8 address bits of breakpoint 4.12.5 DM breakpoint register 2 high byte (DM_BKR2H) Address: 7F94h...
Page 30: Dm Control Register 1 (Dm_Cr1)
Debug module (DM) UM0470 4.12.7 DM control register 1 (DM_CR1) Address: 7F96h Reset value: 0000 0000 (00h) WDGOFF Reserved BC[2:0] Reserved WDGOFF Watchdog control enable. This bit must be set or cleared by software before the watchdogs (WWDG and/or IWDG) are activated. This bit has no effect if the hardware watchdog option is Bit 7 selected.
Page 31: Dm Control Register 2 (Dm_Cr2)
UM0470 Debug module (DM) 4.12.8 DM control register 2 (DM_CR2) Address: 7F97h Reset value: 0000 0000 (00h) Reserved FV_ROM Reserved FV_RAM Bit 7:3 These bits are reserved and must be kept at 0. FV_ROM Remap vector table in ROM. This bit is set or cleared by software. It remaps the vector table to a ROM location Bit 2 (product dependent) instead of program memory (usually 8000h).
Page 32: Dm Control/Status Register 1 (Dm_Csr1)
Debug module (DM) UM0470 4.12.9 DM control/status register 1 (DM_CSR1) Address: 7F98h Reset value: 0001 0000 (10h) Reserved BK2F BK1F Reserved Bit 7 Reserved. STE Step mode enable (read / write) This bit is set and cleared by software. It enables the Step mode. Bit 6 0: Step mode disabled 1: Step mode enabled...
Page 33: Dm Control/Status Register 2 (Dm_Csr2)
UM0470 Debug module (DM) 4.12.10 DM control/status register 2 (DM_CSR2) Address: 7F99h Reset value: 0000 0000 (00h) Reserved SWBRK SWBKF STALL Reserved FLUSH Bits 7:6 Reserved. It must be kept at 0 SWBKE Software breakpoint control bit (read/write) This bit is used to enable/disable the software breakpoint capability with NOP instruction Bit 5 0: DM does not generate any event when NOP(SW BRK) instruction is fetched by the...
Page 34: Dm Enable Function Register (Dm_Enfctr)
Debug module (DM) UM0470 4.12.11 DM enable function register (DM_ENFCTR) Address: 7F9Ah Reset Value: 1111 1111 (FFh) ENFCT7 ENFCT6 ENFCT5 ENFCT4 ENFCT3 ENFCT2 ENFCT1 ENFCT0 ENFCTx Enable function This bit is set and cleared by software. it allows to freeze a particular function of a peripheral when the core is stalled.
Page 35: Summary Of Swim, Dm And Core Register Maps
UM0470 Debug module (DM) 4.12.12 Summary of SWIM, DM and core register maps Table 5. STM8 MCU registers STM8 Register address name 7F00h Reset value 7F01h PC23 PC22 PC21 PC20 PC19 PC18 PC17 PC16 7F02h PC15 PC14 PC13 PC12 PC11...
Page 36 Debug module (DM) UM0470 Table 5. STM8 MCU registers (continued) STM8 Register address name Reserved DM_CSR2 Reserved SWBKE SWBKF STALL Reserved FLUSH 7F99h Reset value DM_ENFCTR ENFCT7 ENFCT6 ENFCT5 ENFCT4 ENFCT3 ENFCT2 ENFCT1 ENFCT0 7F9Ah Reset value The reset value for the SP and PC registers is product dependent. Refer to the device datasheet for more details...
Page 37: Appendix A Description Of The Dm_Enfctr Register
UM0470 Description of the DM_ENFCTR register for each STM8 product Appendix A Description of the DM_ENFCTR register for each STM8 product Some peripherals can be frozen through the debug module during the debug and while using the DM_ENFCTR register (address: 7F9Ah).
Page 38: Revision History
Figure 9: Data format (target -> host) Figure 11: Debug module block diagram Figure 12: STM8 MCU instruction model Figure 13: STM8 Debug module stall timing Figure 14: STM8 DM data breaktiming Figure 15: STM8 DM instruction break timing Figure 16: STM8 DM step timing...
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