Emerson PACSystems RX3i User Manual page 121

PACSystems™ RX3i and RSTi-EP CPU Reference Manual
GFK-2222AK
4.10.3.1.2 CPU Memory Validation
The next phase of system power-up is the validation of the CPU memory. First, if the
system verifies that user memory areas are still valid. A known area of user memory is
checked to determine if data was preserved. Next, if a ladder diagram program exists, a
checksum is calculated across the _MAIN ladder block. If no ladder diagram program
exists, a checksum is calculated across the smallest standalone C program.
When the system is sure that the user memory is preserved, a known area of the bit cache
area is checked to determine if the bit cache data was preserved. If this test passes, the Bit
Cache memory is left containing its power-up values. (Non-retentive outputs are cleared
on a transition from STOP Mode to RUN Mode.) If the checksum is not valid or the
retentive test on the user memory fails, the bit cache memory is assumed to be in error
and all areas are cleared. The CPU is now in a cleared state, the same as if a new CPU
module were installed. All logic and configuration files must be stored from the
programmer to the CPU.
4.10.3.1.3 System Configuration
After completing its self-test, the CPU performs the system configuration. It first clears all
system diagnostic bits in the bit cache memory. This prevents faults that were present
before power-down but are no longer present from accidentally remaining as faulted.
Then it polls each module in the system for completion of the corresponding self-test.
The CPU reads information from each module, comparing it with the stored
(downloaded) rack/slot configuration information. Any differences between actual
configuration and the stored configuration are logged in the fault tables.
4.10.3.1.4 Intelligent Option Module Self-Test Completion
Intelligent option modules may take a longer time to complete their self-tests than the
CPU due to the time required to test communications media or other interface devices.
As an intelligent option module completes its initial self-tests, it tells the CPU the time
required to complete the remainder of these self-tests. During this time, the CPU
provides whatever additional information the module needs to complete its self-
configuration, and the module continues self-tests and configuration. If the module does
not report back in the time it specified, the CPU marks the module as faulted and makes
an entry in one of the fault tables. When all self-tests are complete, the CPU obtains
reports from the module as generated during that particular module's power-up self-test
and places fault information (if any) in the fault tables.
4.10.3.1.5 Intelligent Option Module Dual Port Interface Tests
After completion of the intelligent option module self-test and results reporting, integrity
tests are jointly performed on the dual-port interface used by the CPU and intelligent
option module for communications. These tests validate that the two modules are able to
pass information back and forth, as well as verify the interrupt and semaphore capabilities
needed by the communications protocol. After dual port interface tests are complete, the
communications messaging system is initialized.
CPU Operation
Section 4
October 2019
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