Figure 4. Evaluation Board Schematic; Figure 5. Pinout - Analog Devices AD5258 User Manual

Evaluation Board User Manual
1
J1
13 DGND joints AGND at one point in PCB
D 25
DGND
12
24
11
23
R7
10
22
100
9
21
8
20
7
19
6
18
5
17
4 SCL
16
R6
3
15
100
R5
2
14
100
1
C
SDA_W
SDA_R
DB25
* Jumper Defaults ON
B
A
1

Figure 4. Evaluation Board Schematic

1
W 10 A
AD5259
2 9
AD0 B
3 8
AD1 VDD
TOP VIEW
(Not to Scale)
4 7
SDA G N D
5 6
SCL VLOGIC

Figure 5. Pinout

Rev. C 11/23/04
2
VDD
JPPOWER
C1
10u
* AGND
JPVLOGIC
JPVDD
R2 R3
R1
2.2k 2.2k
2.2k
U2
1 14
1A VCC
2 13
1Y 6A
3 12
2A 6Y
4 11
2Y 5A
5 10
3A 5Y
6 9
3Y 4A
7 8
GND 4Y
SN74HC05
C6
0.1u
U3
1 8
A0 VCC
2 7
A1 WP
3 6
A2 SCL
4 5
GND SDA
AT24C02
V+
JPV+
C3
C7
10u
0.1u
JPBUFFER
-IN Cc
JP3
Rin Rfb
1
NC NC
JP2
2
-IN V+
JP1
3
+IN OUT
4
V- NC
+IN
U4 AD8531/OP1177
C4
C8
JPGND
10u
0.1u
V-
2
64/256-Position I
Digital Potentiometer
3
VLOGIC
C2
10u
*
R4
2.2k
W
U1
1
W A
2
AD0 B
3
AD1 VDD
4
SDA GND
5
SCL Vlogic
AD5258/AD5259
SCL_M ON SDA_M ON
8
7
6
OUT
5
3
2
C Compatible
Nonvolatile Memory
AD5258/AD5259
10 A
9 B
8
7 C5
6
0.1u