NXP Semiconductors MKS22FN256VLH12 Manuals

Manuals and User Guides for NXP Semiconductors MKS22FN256VLH12. We have 1 NXP Semiconductors MKS22FN256VLH12 manual available for free PDF download: Reference Manual

NXP Semiconductors MKS22FN256VLH12 Reference Manual (1375 pages)

Brand: NXP Semiconductors | Category: Computer Hardware | Size: 11 MB

Table of Contents
3
About this Manual
51
Audience
51
Organization
51
Module Descriptions
51
Example: Chip-Specific Information that Supersedes Content in the same Chapter
52
Example: Chip-Specific Information that Refers to a Different Chapter
53
Register Descriptions
54
Conventions
55
Numbering Systems
55
Typographic Notation
55
Special Terms
56
Introduction
57
Overview
57
Kinetis KS Series Feature Summary
57
Block Diagram
61
Module Functional Categories
62
ARM® Cortex®-M4 Core Modules
62
System Modules
63
Memories and Memory Interfaces
64
Clocks
64
Security and Integrity Modules
65
Analog Modules
65
Timer Modules
66
Communication Interfaces
66
Human-Machine Interfaces
67
Orderable Part Numbers
67
Core Overview
69
ARM Cortex-M4 Core Configuration
69
Buses, Interconnects, and Interfaces
70
System Tick Timer
70
Debug Facilities
71
Core Privilege Levels
71
Nested Vectored Interrupt Controller (NVIC) Configuration
71
Interrupt Priority Levels
72
Non-Maskable Interrupt
72
Interrupt Channel Assignments
72
Asynchronous Wake-Up Interrupt Controller (AWIC) Configuration
77
Wake-Up Sources
78
FPU Configuration
79
JTAG Controller Configuration
79
Memories and Memory Interfaces
81
Flash Memory Configuration
81
Flash Memory Types
81
Flash Memory Sizes
82
Flash Security
82
Flash Program Restrictions
82
Flash Modes
82
Erase All Flash Contents
82
FTF_FOPT Register
83
Flash Memory Controller Configuration
83
Number of Masters
83
SRAM Configuration
84
SRAM Sizes
84
KS22/KS20 Sub-Family Reference Manual , Rev. 3, May
84
SRAM Retention in Low Power Modes
85
System Register File Configuration
85
System Register File
85
VBAT Register File Configuration
86
VBAT Register File
86
Memory Map
87
Introduction
87
System Memory Map
87
Aliased Bit-Band Regions
88
Flash Access Control Introduction
90
Flash Memory Map
90
Alternate Non-Volatile IRC User Trim Description
91
SRAM Memory Map
91
Peripheral Bridge (AIPS-Lite) Memory Map
91
Read-After-Write Sequence and Required Serialization of Memory Operations
92
Peripheral Bridge 0 (AIPS-Lite 0) Memory Map
92
Private Peripheral Bus (PPB) Memory Map
96
Clock Distribution
97
Introduction
97
Programming Model
97
High-Level Device Clocking Diagram
97
Clock Definitions
98
Device Clock Summary
99
Internal Clocking Requirements
102
Clock Divider Values after Reset
103
VLPR Mode Clocking
104
Clock Gating
104
Module Clocks
104
PMC 1-Khz LPO Clock
106
IRC 48Mhz Clock
106
WDOG Clocking
107
Debug Trace Clock
108
PORT Digital Filter Clocking
108
LPTMR Clocking
109
RTC_CLKOUT and CLKOUT32K Clocking
109
USB FS OTG Controller Clocking
110
UART Clocking
111
LPUART0 Clocking
111
I2S/SAI Clocking
112
Flexio Clocking
113
LPI2C Clocking
113
TPM Clocking
114
Flexcan Clocking
115
Reset and Boot
117
Introduction
117
Reset
117
Power-On Reset (POR)
118
System Reset Sources
118
MCU Resets
122
Reset Pin
123
Debug Resets
123
Boot
125
Boot Sources
125
Boot Options
125
FOPT Boot Options
125
Boot Sequence
126
Power Management
129
Introduction
129
Clocking Modes
129
Partial Stop
129
DMA Wakeup
130
Compute Operation
131
Peripheral Doze
132
Clock Gating
133
Power Modes Description
133
Entering and Exiting Power Modes
135
Power Mode Transitions
136
Power Modes Shutdown Sequencing
137
Flash Program Restrictions
138
Module Operation in Low Power Modes
138
Security
143
Introduction
143
Flash Security
143
Security Interactions with Other Modules
144
Security Interactions with Debug
144
Debug
145
Introduction
145
References
146
The Debug Port
146
JTAG-To-SWD Change Sequence
147
JTAG-To-Cjtag Change Sequence
147
Debug Port Pin Descriptions
148
System TAP Connection
148
IR Codes
149
JTAG Status and Control Registers
149
MDM-AP Control Register
150
MDM-AP Status Register
151
Debug Resets
153
Ahb-Ap
154
Itm
154
Core Trace Connectivity
155
Tpiu
155
Dwt
155
Debug in Low Power Modes
156
Debug Module State in Low Power Modes
156
Debug & Security
157
Signal Multiplexing and Signal Descriptions
159
Introduction
159
Pinout
159
Signal Multiplexing and Pin Assignments
159
Pinouts
163
Module Signal Description Tables
166
Core Modules
167
System Modules
167
Clock Modules
168
Analog
168
Timer Modules
169
Communication Interfaces
170
Human-Machine Interfaces (HMI)
174
Port Control and Interrupts (PORT)
175
Chip-Specific Information for this Module
175
Signal Multiplexing Integration
175
Introduction
177
Overview
177
Features
177
Modes of Operation
178
External Signal Description
179
Detailed Signal Description
179
Memory Map and Register Definition
180
Pin Control Register N (Portx_Pcrn)
186
Global Pin Control Low Register (Portx_Gpclr)
189
Global Pin Control High Register (Portx_Gpchr)
189
Interrupt Status Flag Register (Portx_Isfr)
190
Digital Filter Enable Register (Portx_Dfer)
190
Digital Filter Clock Register (Portx_Dfcr)
191
Digital Filter Width Register (Portx_Dfwr)
191
Functional Description
192
Pin Control
192
Global Pin Control
193
External Interrupts
193
Digital Filter
194
System Integration Module (SIM)
197
Introduction
197
Features
197
Memory Map and Register Definition
198
System Options Register 1 (SIM_SOPT1)
199
System Options Register 2 (SIM_SOPT2)
200
System Options Register 5 (SIM_SOPT5)
202
System Options Register 7 (SIM_SOPT7)
204
System Options Register 9 (SIM_SOPT9)
205
System Device Identification Register (SIM_SDID)
207
System Clock Gating Control Register 4 (SIM_SCGC4)
209
System Clock Gating Control Register 5 (SIM_SCGC5)
211
System Clock Gating Control Register 6 (SIM_SCGC6)
212
System Clock Gating Control Register 7 (SIM_SCGC7)
216
System Clock Divider Register 1 (SIM_CLKDIV1)
216
System Clock Divider Register 2 (SIM_CLKDIV2)
218
Flash Configuration Register 1 (SIM_FCFG1)
219
Flash Configuration Register 2 (SIM_FCFG2)
221
Unique Identification Register High (SIM_UIDH)
221
Unique Identification Register MID-High (SIM_UIDMH)
222
Unique Identification Register MID Low (SIM_UIDML)
222
Unique Identification Register Low (SIM_UIDL)
223
System Clock Divider Register 3 (SIM_CLKDIV3)
223
Miscellaneous Control Register (SIM_MISCCTL)
224
Functional Description
225
Kinetis Flashloader
227
Chip-Specific Information for this Module
227
Introduction
228
Functional Description
229
Memory Maps
229
Start-Up Process
230
Clock Configuration
232
Flashloader Protocol
232
Flashloader Packet Types
237
Flashloader Command API
244
Peripherals Supported
264
I2C Peripheral
264
SPI Peripheral
266
UART Peripheral
268
USB Peripheral
270
CAN (or Flexcan) Peripheral
273
Get/Setproperty Command Properties
275
Property Definitions
276
Kinetis Flashloader Status Error Codes
278
Reset Control Module (RCM)
281
Introduction
281
Reset Memory Map and Register Descriptions
281
System Reset Status Register 0 (RCM_SRS0)
282
System Reset Status Register 1 (RCM_SRS1)
283
Reset Pin Filter Control Register (RCM_RPFC)
285
Reset Pin Filter Width Register (RCM_RPFW)
286
Sticky System Reset Status Register 0 (RCM_SSRS0)
287
Sticky System Reset Status Register 1 (RCM_SSRS1)
289
System Mode Controller (SMC)
291
Introduction
291
Modes of Operation
291
Memory Map and Register Descriptions
293
Power Mode Protection Register (SMC_PMPROT)
294
Power Mode Control Register (SMC_PMCTRL)
295
Stop Control Register (SMC_STOPCTRL)
297
Power Mode Status Register (SMC_PMSTAT)
298
Functional Description
299
Power Mode Transitions
299
Power Mode Entry/Exit Sequencing
302
Run Modes
304
Wait Modes
306
Stop Modes
306
Debug in Low Power Modes
310
Power Management Controller (PMC)
311
Introduction
311
Features
311
Low-Voltage Detect (LVD) System
311
LVD Reset Operation
312
LVD Interrupt Operation
312
Low-Voltage Warning (LVW) Interrupt Operation
312
High-Voltage Detect (HVD) System
313
HVD Reset Operation
313
HVD Interrupt Operation
313
I/O Retention
314
Memory Map and Register Descriptions
314
Low Voltage Detect Status and Control 1 Register (PMC_LVDSC1)
315
Low Voltage Detect Status and Control 2 Register (PMC_LVDSC2)
316
Regulator Status and Control Register (PMC_REGSC)
317
High Voltage Detect Status and Control 1 Register (PMC_HVDSC1)
319
Chip-Specific Information for this Module
321
Wake-Up Sources
321
Introduction
322
Low-Leakage Wakeup Unit (LLWU)
323
Features
323
Modes of Operation
323
Block Diagram
324
LLWU Signal Descriptions
325
Memory Map/Register Definition
326
LLWU Pin Enable 1 Register (LLWU_PE1)
327
LLWU Pin Enable 2 Register (LLWU_PE2)
328
LLWU Pin Enable 3 Register (LLWU_PE3)
329
LLWU Pin Enable 4 Register (LLWU_PE4)
330
LLWU Pin Enable 5 Register (LLWU_PE5)
331
LLWU Pin Enable 6 Register (LLWU_PE6)
332
LLWU Pin Enable 7 Register (LLWU_PE7)
334
LLWU Pin Enable 8 Register (LLWU_PE8)
335
LLWU Module Enable Register (LLWU_ME)
336
LLWU Pin Flag 1 Register (LLWU_PF1)
337
LLWU Pin Flag 2 Register (LLWU_PF2)
339
LLWU Pin Flag 3 Register (LLWU_PF3)
341
LLWU Pin Flag 4 Register (LLWU_PF4)
342
LLWU Module Flag 5 Register (LLWU_MF5)
344
LLWU Pin Filter 1 Register (LLWU_FILT1)
346
LLWU Pin Filter 2 Register (LLWU_FILT2)
347
Functional Description
348
LLS Mode
349
VLLS Modes
349
Initialization
349
Miscellaneous Control Module (MCM)
351
Introduction
351
Features
351
Memory Map/Register Descriptions
351
Crossbar Switch (AXBS) Slave Configuration (MCM_PLASC)
352
Crossbar Switch (AXBS) Master Configuration (MCM_PLAMC)
352
Crossbar Switch (AXBS) Control Register (MCM_PLACR)
353
Interrupt Status and Control Register (MCM_ISCR)
353
Compute Operation Control Register (MCM_CPO)
356
Functional Description
357
Interrupts
357
Crossbar Switch Lite (AXBS-Lite)
359
Chip-Specific Information for this Module
359
Crossbar-Lite Switch Master Assignments
359
Crossbar-Lite Switch Slave Assignments
359
Introduction
359
Features
360
Memory Map / Register Definition
360
Functional Description
360
General Operation
360
Arbitration
361
Initialization/Application Information
363
Peripheral Bridge (AIPS-Lite)
365
Chip-Specific Information for this Module
365
Number of Peripheral Bridges
365
Memory Maps
365
Introduction
365
Features
365
General Operation
366
Memory Map/Register Definition
366
Functional Description
366
Access Support
366
Direct Memory Access Multiplexer (DMAMUX)
367
Chip-Specific Information for this Module
367
DMA MUX Request Sources
367
DMA Transfers Via PIT Trigger
369
Introduction
369
Overview
369
Features
370
Modes of Operation
370
External Signal Description
371
Memory Map/Register Definition
371
Endianness
371
Channel Configuration Register (Dmamux_Chcfgn)
372
Functional Description
373
DMA Channels with Periodic Triggering Capability
374
DMA Channels with no Triggering Capability
376
Always-Enabled DMA Sources
376
Initialization/Application Information
377
Reset
377
Enabling and Configuring Sources
377
Enhanced Direct Memory Access (Edma)
381
Introduction
381
Edma System Block Diagram
381
Block Parts
382
Features
383
Modes of Operation
384
Memory Map/Register Definition
385
TCD Memory
385
TCD Initialization
385
TCD Structure
386
Reserved Memory and Bit Fields
386
Control Register (DMA_CR)
397
Error Status Register (DMA_ES)
400
Enable Request Register (DMA_ERQ)
402
Enable Error Interrupt Register (DMA_EEI)
404
Clear Enable Error Interrupt Register (DMA_CEEI)
406
Set Enable Error Interrupt Register (DMA_SEEI)
407
Clear Enable Request Register (DMA_CERQ)
408
Set Enable Request Register (DMA_SERQ)
409
Clear DONE Status Bit Register (DMA_CDNE)
410
Set START Bit Register (DMA_SSRT)
411
Clear Error Register (DMA_CERR)
412
Clear Interrupt Request Register (DMA_CINT)
413
Interrupt Request Register (DMA_INT)
414
Error Register (DMA_ERR)
416
Hardware Request Status Register (DMA_HRS)
419
Enable Asynchronous Request in Stop Register (DMA_EARS)
422
Channel N Priority Register (Dma_Dchprin)
424
TCD Source Address (Dma_Tcdn_Saddr)
425
TCD Signed Source Address Offset (Dma_Tcdn_Soff)
425
TCD Transfer Attributes (Dma_Tcdn_Attr)
426
TCD Minor Byte Count (Minor Loop Mapping Disabled) (Dma_Tcdn_Nbytes_Mlno)
427

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NXP Semiconductors MKS22FN256VLH12 Reference Manual (1375 pages)

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