Evaluation Board Schematics And Artwork - Analog Devices EVAL-AD5423SDZ User Manual

EVAL-AD5423SDZ

EVALUATION BOARD SCHEMATICS AND ARTWORK

C16
0.1UF
AD0
IN
AD1
IN
/RESET
IN
SCLK
IN
SDI
IN
R9
/SYNC
IN
13.7K
C_HART
IN
/LDAC
IN
REFIN
Evaluation Board User Guide
AVDD2
IN
AVDD1
IN
C15
0.1UF
C18 GND
4.7UF
GND
23
AD0
22
AD1
16
RESET
19
SCLK
20
SDI
21
SYNC
8
RSETB
R B
7
RSETA
R A
11
IN
C HART
17
LDAC
9
REFIN
AD5423BCPZ
AVSS
IN
0.1UF
C14C17
50V
Figure 15.
VLOGIC
IN
C13
0.1UF
GND
0.1UF
U2
12
VLDO
14
SDO
24
FAULT
28
+V SENSE
29
VI OUT
26
-V SENSE
27
CCOMP
C COMP
10
REFOUT
R1
0
REFGND GNDGND
AVSS
IN
A
4.7UF
C
D2
GND
GND
AD5423 Device Schematic
Rev. 0 | Page 13 of 19
VLDO
1 RED
C12
VLOGIC
IN
R5
GND 1K
A
DS1
SDO
OUT
C
+VSENSE
IN
IN
-VSENSE
THROUGH-HOLE C_COMP IN GOLD PINS
OUT
REFOUT
C10
DNI 2.2UF
OPTIONAL RC FILTER ON REFOUT
REFGND
UG-1554
OUT
VLDO
VF = 1.8V
IF = 2MA
OUT
/FAULT
OUT
VI_OUT