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External Bus Cycles
Flash Memory
Architecture
AT89C5131A-L
28
Table 33. External Data Memory Interface Signals
Signal
Name
Type
Description
Address Lines
A15:8
O
Upper address lines for the external bus.
Address/Data Lines
AD7:0
I/O
Multiplexed lower address lines and data for the external memory.
Address Latch Enable
ALE
O
ALE signals indicates that valid address information are available on lines
AD7:0.
Program Store Enable Output
PSEN
O
This signal is active low during external code fetch or external code read
(MOVC instruction).
This section describes the bus cycles the AT89C5131A-L executes to fetch code (see
Figure 15) in the external program/code memory.
External memory cycle takes 6 CPU clock periods. This is equivalent to 12 oscillator
clock periods in standard mode or 6 oscillator clock periods in X2 mode. For further
information on X2 mode (see the clock Section).
For simplicity, the accompanying figure depicts the bus cycle waveforms in idealized
form and do not provide precise timing information.
Figure 15. External Code Fetch Waveforms
CPU Clock
ALE
PSEN
P0
D7:0
P2
PCH
AT89C5131A-L features two on-chip Flash memories:
•
Flash memory FM0:
containing 32 Kbytes of program memory (user space) organized into 128-byte
pages,
•
Flash memory FM1:
3 Kbytes for bootloader and Application Programming Interfaces (API).
The FM0 supports both parallel programming and Serial In-System Programming (ISP)
whereas FM1 supports only parallel programming by programmers. The ISP mode is
detailed in the "In-System Programming" section.
All Read/Write access operations on Flash memory by user application are managed by
a set of API described in the "In-System Programming" section.
PCL
D7:0
PCH
Alternate
Function
P2.7:0
P0.7:0
PCL
D7:0
PCH
4338F–USB–08/07
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