Write Operations - Analog Devices dBCool ADT7467 Manual

ADT7467
1
SCL
0 1
SDA
START BY
MASTER
1
SCL
0 1
SDA
START BY
MASTER
It is possible to read a data byte from a data register without
first writing to the address pointer register, if the address
pointer register is already at the correct value. However, it is not
possible to write data to a register without writing to the address
pointer register, because the first data byte of a write is always
written to the address pointer register.
In addition to supporting the send byte and receive byte
protocols, the ADT7467 also supports the read byte protocol.
(See System Management Bus Specifications Rev. 2 for more
information. This document is available from Intel.)
If several read or write operations must be performed in
succession, the master can send a repeat start condition instead
of a stop condition to begin a new operation.

WRITE OPERATIONS

The SMBus specification defines several protocols for different
types of read and write operations. The ones used in the
ADT7467 are discussed below. The following abbreviations are
used in the diagrams:
S – START
P – STOP
R – READ
W – WRITE
A – ACKNOWLEDGE
A – NO ACKNOWLEDGE
The ADT7467 uses the following SMBus write protocols.
Send Byte
In this operation, the master device sends a single command
byte to a slave device as follows:
1. The master device asserts a start condition on SDA.
0 1 0
1 1
FRAME 1
SERIAL BUS ADDRESS BYTE
Figure 17. Writing to the Address Pointer Register Only
0 1 0
1 1
FRAME 1
SERIAL BUS ADDRESS BYTE
Figure 18. Reading Data from a Previously Selected Register
9 1
D7 D6 D4
R/W D5
ACK. BY
ADT7467
ADDRESS POINTER REGISTER BYTE
9 1
D7 D6
R/W D5
ACK. BY
ADT7467
DATA BYTE FROM ADT7467
2. The master sends the 7-bit slave address followed by the
write bit (low).
3. The addressed slave device asserts ACK on SDA.
4. The master sends a command code.
5. The slave asserts ACK on SDA.
6. The master asserts a stop condition on SDA and the
transaction ends.
For the ADT7467, the send byte protocol is used to write a
register address to RAM for a subsequent single byte read from
the same address. This operation is illustrated in Figure 19.
Figure 19. Setting a Register Address for Subsequent Read
If the master is required to read data from the register
immediately after setting up the address, it can assert a repeat
start condition immediately after the final ACK and carry out a
single byte read without asserting an intermediate stop
condition.
Write Byte
In this operation, the master device sends a command byte and
one data byte to the slave device, as follows:
1. The master device asserts a start condition on SDA.
2. The master sends the 7-bit slave address followed by the
write bit (low).
3. The addressed slave device asserts ACK on SDA.
4. The master sends a command code.
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9
D3 D2 D1
D0
ACK. BY
ADT7467
FRAME 2
D4 D3 D2 D1
D0
NO ACK. BY
MASTER
FRAME 2
1 2 3 4
SLAVE REGISTER
S W A
ADDRESS ADDRESS
STOP BY
MASTER
9
STOP BY
MASTER
5 6
A P