Analog Devices dBCool ADT7467 Manual page 24

ADT7467
Generating SMBALERT Interrupts from THERM Timer
Events
The ADT7467 can generate SMBALERT s when a programma-
ble THERM timer limit has been exceeded. This allows the
system designer to ignore brief, infrequent THERM assertions,
while capturing longer THERM timer events. Register 0x7A is
the THERM timer limit register. This 8-bit register allows a
limit from 0 s (first THERM assertion) to 5.825 s to be set
before an SMBALERT is generated. The THERM timer value is
compared with the contents of the THERM timer limit register.
If the THERM timer value exceeds the THERM timer limit
728.32ms
THERM
364.16ms
TIMER LIMIT
182.08ms
(REG. 0x7A)
2.914s
1.457s
91.04ms
45.52ms
22.76ms
0 1 2 3 4 5 6 7
COMPARATOR
Figure 32. Functional Block Diagram of ADT7467's THERM Monitoring Circuitry
value, then the F4P bit (Bit 5) of Status Register 2 is set, and an
SMBALERT is generated. Note that the F4P bit (Bit 5) of Mask
Register 2 (Reg. 0x75) masks out SMBALERT s, if this bit is set
to 1; although the F4P bit of Interrupt Status Register 2 still is
set, if the THERM timer limit is exceeded.
Figure 32 is a functional block diagram of the THERM timer,
limit, and associated circuitry. Writing a value of 0x00 to the
THERM timer limit register (Reg. 0x7A) causes SMBALERT to
be generated on the first THERM assertion. A THERM timer
limit value of 0x01 generates an SMBALERT , once cumulative
THERM assertions exceed 45.52 ms.
2.914s
1.457s
728.32ms
364.16ms
182.08ms
91.04ms
45.52ms
22.76ms
7 6 5 4 3 2 1 0
THERM TIMER CLEARED ON READ
F4P BIT (BIT 5)
IN
OUT
STATUS REGISTER 2
LATCH
RESET
CLEARED
1 = MASK
ON READ
F4P BIT (BIT 5)
MASK REGISTER 2
(REG. 0x75)
Rev. 0 | Page 24 of 80
THERM TIMER
(REG. 0x79)
THERM
SMBALERT