Analog Devices dBCool ADT7467 Manual page 4

ADT7467
Parameter
OPEN-DRAIN DIGITAL OUTPUTS, PWM1 to PWM3, XTO
Current Sink, I
OL
Output Low Voltage, V
OL
High Level Output Current, I
OPEN-DRAIN SERIAL DATA BUS OUTPUT (SDA)
Output Low Voltage, V
OL
High Level Output Current, I
SMBUS DIGITAL INPUTS (SCL, SDA)
Input High Voltage, V
IH
Input Low Voltage, V
IL
Hysteresis
DIGITAL INPUT LOGIC LEVELS (TACH INPUTS)
Input High Voltage, V
IH
Input Low Voltage, V
IL
Hysteresis
DIGITAL INPUT LOGIC LEVELS (THERM) ADTL+
Input High Voltage, V
IH
Input Low Voltage, V
IL
DIGITAL INPUT CURRENT
Input High Current, I
IH
Input Low Current, I
IL
Input Capacitance, C
IN
SERIAL BUS TIMING 5
Clock Frequency, f
SCLK
Glitch Immunity, t
SW
Bus Free Time, t
BUF
Start Setup Time, t
SU;STA
Start Hold Time, t
HD;STA
SCL Low Time, t
LOW
SCL High Time, t
HIGH
SCL, SDA Rise Time, t
R
SCL, SDA Fall Time, t
F
Data Setup Time, t
SU;DAT
Data Hold Time, t
HD;DAT
Detect Clock Low Timeout, t
SCL
t
HD; STA
SDA
t
BUF
P S
Min
OH
OH
2.0
2.0
−0.3
−1
10
4.7
4.7
4.0
4.7
4.0
250
300
15
TIMEOUT
t t
R F
t
LOW
t
HIGH
t
HD; DAT
Figure 2. Serial Bus Timing Diagram
Typ Max
8.0
0.4
0.1 1.0
0.4
0.1 1.0
0.4
500
5.5
0.8
0.5
0.75 × V
CCP
0.4
1
5
400
50
50
1000
300
35
t
SU; STA
t
SU; DAT
S
Rev. 0 | Page 4 of 80
Unit Test Conditions/Comments
mA
V I = −8.0 mA, V = +3.3 V
OUT CC
µA V = V
OUT CC
V I = −4.0 mA, V = +3.3 V
OUT CC
µA V = V
OUT CC
V
V
mV
V
V Maximum input voltage
V
V Minimum input voltage
V p-p
V
V
µA V = V
IN CC
µA V = 0
IN
pF
See Figure 2
kHz
ns
µs
µs
µs
µs
µs
ns
µs
ns
ns
ms Can be optionally disabled
t
HD; STA
t
SU; STO
P