Fujitsu F2MC-16L Series User Manual page 12

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Address Area
8000..FFFF
2000..7FFF
0D00..1FFF
0100..0CFF
00C0..00FF
0000..00BF
Fig. 3: Memory area 000000..00FFFFh. This page is accessed when
address bits 16..23 (20..23 not output by the controller) are all
zero. The addresses 00xxxxh access this page. However,
10xxxxh accesses the complete external page 0.
In User Mode 1 (sub-mode "a" and "b") RAM 0 is mapped to page 0, so RAM 0 can be
accessed as well on external page 0 as within the external I/O area and upper area on absolute
page 0. In return for it Module 0 is mapped on page E. In sub-mode "b" this area is enlarged to
128 KB so that Module 1 could be accessed on page F.
The RAM on page 0 (in User Mode 1) might be used for accessing the external I/O-area. A
program fixed on ROM (including its own interrupt vector table and plugged as Module 1)
could be started in User Mode 1b by pressing User Reset button.
The low active signal EXP (expansion) set by the Evaluation Board peripherals might be used
to select the remaining external memory area not occupied by the board itself. These signals
( EXP, the module chip selects CSx , the address bus provided by the Evaluation Board and the
address/data bus, the bus control signals provided by the controller itself) might be used for
system expansions.
Eight control bank register and four switches control the evaluation board and its memory
mapping. Three jumpers are needed for further functionality. The control bank register resides
at physical page 7 (see fig. 4). The four switches are placed left beside the Power and the User
RUN LED (see fig. 1).
15
Address
x7xxx0H
x7xxx2H
x7xxx4H
x7xxx6H
x7xxx8H
x7xxxAH
x7xxxCH
Fig. 4: The eight registers of the Evaluation Board control bank
- 12 -
FUJITSU MB90675-Evaluation Board - User Manual
Absolute Page 0'
Monitor
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(inclusive EI²OS -descriptors and generall register
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Evaluation Board Control Bank
monitor mode
user mode
RUN LED
user LED
UART data
UART status
left display
right display
(MB90678)
User0
User1a
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external
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no access
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internal RAM
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external
banks)
RAM0
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AA
controller peripherals
0
0
r/w bit 0
monitor user mapping
user0 user1 mapping
r/w bit 0
on
r/w bit 0
off
r/w bit 0
r/w
external UART data register
r/w
external UART status register
w
left & right LED display
© FUJITSU Mikroelektronik GmbH 1996
User1b
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I/O
1
off activ user
on user LED

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