Texas Instruments DLP Discovery 4100 User Manual page 11

www.ti.com
2.3.12.5 REG. 1.8 V
This delivers 3 A at 1.8 V for the DDR2 supply and FPGA I/O.
2.3.12.6 REG. 2.5 V
This delivers 6 A at 2.5 V to supply the XCF16P FPGA I/O.
2.3.12.7 REG. 3.3 V
This delivers 3 A at 3.3 V to supply the DMD and USB controller.
2.3.12.8 REG. 12 V
This delivers the 0.5 A at 12 V to supply the DLPA200.
DLPU040B – OCTOBER 2016 – REVISED MARCH 2023
Submit Document Feedback
Copyright © 2023 Texas Instruments Incorporated
®
DLP Discovery™ 4100 Development Platform
Overview
11