Measurement Computing CIO-DAS6402/12 Manual page 23

SEDIFF - Analog input channel configuration, 0 = differential, 1 = single ended.
MA3:0 - Analog input channel mux setting (for next conversion).
WRITE
7 6
1/10MHz POSTMODE
ENHANCED MODE:
The write functions of the status register are to clear certain flip-flop states, and set the Pacer clock to 1 or 10 MHz.
CLRINT - Clear Interrupt flip-flop when = 1. No action when = 0.
CLRXTR - Clear External Trigger flip-flop when = 1. No action when = 0
CLRXIN - Clear External Interrupt flip-flop when = 1. No action when = 0.
(These 'Clear' functions get automatically reset to 0 in 1 to 2 µsec).
EXTEND - Qualifier for bits 5 to 7 data. Must be set to 1 prior to setting the desired bits at 5 to 7.
=0, any data at bits 5 to 7 will be ignored and the state of the bit will not change.
The MODE bit must be = 1 (Enhanced) to change the EXTEND bit.
Example: to set the 1/10MHz bit to set the Pacer time base to 10MHz:
Do each step as separate write operations:
1. Set MODE bit to 1 (base + B, bit 4)
2. Set EXTEND to 1 (base + 8, bit 4)
3. Set 1/10 bit to 1 (base + 8, bit 7), be sure to leave bit 4 set as well, including bits 5/6 if desired to leave them set.
4. Set EXTEND bit to 0, leave the bits in 5 to 7 set as required.
After EXTEND bit is zeroed, any writes to bits 5 to 7 are masked off (doesn't change).
Please note that the clear flip-flop bits in 0 to 2 will be active if their corresponding data bits are high during any write to base+8 in
Enhanced Mode.
ARMED - Used with various pre and post-trigger scenarios to gate a 'residual' counter on (CTR0 of the 8254).
Counter 0 operates in Mode 0 and counts conversions, stopping the acquisition process when it reaches terminal count.
When = 0, counting of post-trigger samples is disabled. When =1, counting of post-trigger samples is enabled.
See also POSTMODE.
POSTMODE - Used to select whether FifoHalf Full or ADC convert starts Counter 0. Used in conjunction with
PRETRIG to select a strobe to latch the Counter 0 gate. (See BASE + 10 for PRETRIG.) Refer to Table 6-3.
Total # of counts (N) less- than-or-equal-to FIFO 1/2-full is a special case:
Gate CTR0:
fifo>N>1/2fifo
N>fifo
N <= 1/2 fifo
N> 1/2 fifo
N < =1/2 fifo
1/10MHz - Sets Pacer clock frequency. .
When bit 7 = 1, Forces Pacer clock to 10 MHz. When = 0, forces Pacer clock to 1 MHz.
5 4
ARMED EXTEND
Table 5-3. Post-Mode Operations
Pretrig? POST-MODE
no 0 0
no 0 0
no 0 1
yes 1 0
yes 1 1
3 2
- CLRXIN
Ctr 0 gate strobe:
on last fifo half full
on last fifo half full
1st conversion
on fifo half (last interrupt)
on the external trigger
19
1 0
CLRXTR CLRINT
ARMED bit is set by:
Before acquisition is started
Next to last full 'packet'
Before acquisition is started
ISR on last full 'packet'
Before acquisition is started