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Alinx ZYNQ UltraScale+ AXU3EG User Manual

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ZYNQ UltraScale+
FPGA Development Board
AXU3EG
User Manual

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Summary of Contents for Alinx ZYNQ UltraScale+ AXU3EG

  • Page 1 ZYNQ UltraScale+ FPGA Development Board AXU3EG User Manual...

  • Page 2: Version Record

    ZYNQ Ultrascale + FPGA Board AXU3EG User Manual Version Record Version Date Release By Description Rev 1.0 2021-03-27 Rachel Zhou First Release www.alinx.com 2 / 57...

  • Page 3: Table Of Contents

    Part 3.8: Expansion Header ............. 45 Part 3.9: CAN communication interface ........... 47 Part 3.10: 485 communication interface ........... 48 Part 3.11: MIPI camera interface ............49 Part 3.12: JTAG Debug Port ............. 50 Part 3.13: Real-time clock ..............51 www.alinx.com 3 / 57...
  • Page 4 Part 3.15: User LEDs ............... 53 Part 3.16: Keys ................. 54 Part 3.17: DIP Switch Configuration ..........54 Part 3.18: Power Supply ..............55 Part 3.19: ALINX Customized Fan ........... 56 Part 3.20: Carrier Board Size Dimension ......... 57 www.alinx.com 4 / 57...
  • Page 5 It is a "professional" ZYNQ development platform. For high-speed data transmission and exchange, pre-verification and post-application of data processing is possible. This product is very suitable for students, engineers and other groups engaged in MPSoCs development. www.alinx.com 5 / 57...

  • Page 6: Part 1: Fpga Development Board Introduction

    1 SD card slot,2-Channel 40-pin expansion header, 2-Channel CAN bus interfaces, 2-Channel RS485 bus interfaces, 1 MIPI Camera Interface and some keys and LEDs. The following figure shows the structure of the entire development system: www.alinx.com 6 / 57...
  • Page 7 1 PCIEx1 standard M.2 interface, used to connect M.2 SSD solid state drives, with a communication speed of up to 6Gbps.  DP Output Interface 1 standard Display Port output display interface, used for video image www.alinx.com 7 / 57...
  • Page 8  40-pin expansion port 2 40-pin 0.1-inch pitch expansion port can be connected to various ALINX modules (binocular camera, TFT LCD screen, high-speed AD module, etc.). The expansion port contains 1-channel 5V power supply, 2-channel 3.3V power supply, 3-channel way ground, 34 IOs port.
  • Page 9 There are 1 power indicator and 1 DONE Configuration indicator on the core board, 1 power indicator on the carrier board. There are 1 power indicator and 2 user indicators on the carrier board.  KEYs 3 KEYs, include 1 Rest KEY and 2 User KEYs. www.alinx.com 9 / 57...

  • Page 10: Part 2: Acu3Eg Core Board

    PL side (HP I/O: 96, HD I/O: 84). The wiring between the CZU3EG chip and the interface has been processed with equal length and differential, and the core board size is only 3.15*2.36 (inch), which is very suitable for secondary development. www.alinx.com 10 / 57...

  • Page 11: Part 2.2: Zynq Chip

    PCIE Gen2, USB3.0, SATA 3.1, DisplayPort; it also supports USB2.0 , Gigabit Ethernet, SD/SDIO, I2C, CAN, UART, GPIO and other interfaces. The PL end contains a wealth of programmable logic units, DSP and internal RAM. . Figure 2-2-1 detailed the Overall Block Diagram of the ZU3EG Chip. www.alinx.com 11 / 57...
  • Page 12 2 CPUs  ARM dual-core Cortex-R5 processor, speed up to 500MHz, each CPU 32KB level 1 instruction and data cache, and 128K tightly coupled memory.  External storage interface, support 32/64bit DDR4/3/3L, LPDDR4/3 interface www.alinx.com 12 / 57...

  • Page 13: Part 2.3: Ddr4 Dram

    PS side to form a 64-bit data bus bandwidth and 4GB capacity. One DDR4 chip is mounted on the PL end, which is a 16-bit data bus width and a capacity of 1GB. The maximum operating speed of the DDR4 SDRAM on the PS side www.alinx.com 13 / 57...
  • Page 14 PCB design to ensure high-speed and stable operation of DDR4. The hardware connection of DDR4 SDRAM on the PS Side is shown in Figure 2-3-1: Figure 2-3-1: DDR3 DRAM schematic diagram www.alinx.com 14 / 57...
  • Page 15 Pin Number PS_DDR4_DQS0_P PS_DDR_DQS_P0_504 AF21 PS_DDR4_DQS0_N PS_DDR_DQS_N0_504 AG21 PS_DDR4_DQS1_P PS_DDR_DQS_P1_504 AF23 PS_DDR4_DQS1_N PS_DDR_DQS_N1_504 AG23 PS_DDR4_DQS2_P PS_DDR_DQS_P2_504 AF25 PS_DDR4_DQS2_N PS_DDR_DQS_N2_504 AF26 PS_DDR4_DQS3_P PS_DDR_DQS_P3_504 AE27 PS_DDR4_DQS3_N PS_DDR_DQS_N3_504 AF27 PS_DDR4_DQS4_P PS_DDR_DQS_P4_504 PS_DDR4_DQS4_N PS_DDR_DQS_N4_504 PS_DDR4_DQS5_P PS_DDR_DQS_P5_504 PS_DDR4_DQS5_N PS_DDR_DQS_N5_504 PS_DDR4_DQS6_P PS_DDR_DQS_P6_504 www.alinx.com 15 / 57...
  • Page 16 AG26 PS_DDR4_DQ21 PS_DDR_DQ21_504 AH25 PS_DDR4_DQ22 PS_DDR_DQ22_504 AH26 PS_DDR4_DQ23 PS_DDR_DQ23_504 AG25 PS_DDR4_DQ24 PS_DDR_DQ24_504 AH27 PS_DDR4_DQ25 PS_DDR_DQ25_504 AH28 PS_DDR4_DQ26 PS_DDR_DQ26_504 AF28 PS_DDR4_DQ27 PS_DDR_DQ27_504 AG28 PS_DDR4_DQ28 PS_DDR_DQ28_504 AC27 PS_DDR4_DQ29 PS_DDR_DQ29_504 AD27 PS_DDR4_DQ30 PS_DDR_DQ30_504 AD28 PS_DDR4_DQ31 PS_DDR_DQ31_504 AC28 PS_DDR4_DQ32 PS_DDR_DQ32_504 www.alinx.com 16 / 57...
  • Page 17 PS_DDR4_DQ53 PS_DDR_DQ53_504 PS_DDR4_DQ54 PS_DDR_DQ54_504 PS_DDR4_DQ55 PS_DDR_DQ55_504 PS_DDR4_DQ56 PS_DDR_DQ56_504 PS_DDR4_DQ57 PS_DDR_DQ57_504 PS_DDR4_DQ58 PS_DDR_DQ58_504 PS_DDR4_DQ59 PS_DDR_DQ59_504 PS_DDR4_DQ60 PS_DDR_DQ60_504 PS_DDR4_DQ61 PS_DDR_DQ61_504 PS_DDR4_DQ62 PS_DDR_DQ62_504 PS_DDR4_DQ63 PS_DDR_DQ63_504 PS_DDR4_DM0 PS_DDR_DM0_504 AG20 PS_DDR4_DM1 PS_DDR_DM1_504 AE23 PS_DDR4_DM2 PS_DDR_DM2_504 AE25 PS_DDR4_DM3 PS_DDR_DM3_504 AE28 PS_DDR4_DM4 PS_DDR_DM4_504 www.alinx.com 17 / 57...
  • Page 18 PS_DDR4_ACT_B PS_DDR_ACT_N_504 PS_DDR4_ALERT_B PS_DDR_ALERT_N_504 PS_DDR4_BA0 PS_DDR_BA0_504 PS_DDR4_BA1 PS_DDR_BA1_504 PS_DDR4_BG0 PS_DDR_BG0_504 PS_DDR4_CS0_B PS_DDR_CS_N0_504 PS_DDR4_ODT0 PS_DDR_ODT0_504 PS_DDR4_PARITY PS_DDR_PARITY_504 PS_DDR4_RESET_B PS_DDR_RST_N_504 PS_DDR4_CLK0_P PS_DDR_CK0_P_504 PS_DDR4_CLK0_N PS_DDR_CK0_N_504 PS_DDR4_CKE0 PS_DDR_CKE0_504 PL Side DDR4 DRAM pin assignment: Signal Name Pin Name Pin Number www.alinx.com 18 / 57...
  • Page 19 PL_DDR4_DQ14 IO_L14N_T2L_N3_GC_64 PL_DDR4_DQ15 IO_L14P_T2L_N2_GC_64 PL_DDR4_DM0 IO_L19P_T3L_N0_DBC_AD9P_64 PL_DDR4_DM1 IO_L13P_T2L_N0_GC_QBC_64 PL_DDR4_A0 IO_L8N_T1L_N3_AD5N_64 PL_DDR4_A1 IO_L3P_T0L_N4_AD15P_64 PL_DDR4_A2 IO_L8P_T1L_N2_AD5P_64 PL_DDR4_A3 IO_L3N_T0L_N5_AD15N_64 PL_DDR4_A4 IO_L11P_T1U_N8_GC_64 PL_DDR4_A5 IO_L4P_T0U_N6_DBC_AD7P_64 PL_DDR4_A6 IO_L9N_T1L_N5_AD12N_64 PL_DDR4_A7 IO_L2P_T0L_N2_64 PL_DDR4_A8 IO_L9P_T1L_N4_AD12P_64 PL_DDR4_A9 IO_L1P_T0L_N0_DBC_64 PL_DDR4_A10 IO_L4N_T0U_N7_DBC_AD7N_64 PL_DDR4_A11 IO_L7N_T1L_N1_QBC_AD13N_64 PL_DDR4_A12 IO_L6N_T0U_N11_AD6N_64 PL_DDR4_A13 IO_L1N_T0L_N1_DBC_64 www.alinx.com 19 / 57...

  • Page 20: Part 2.4: Qspi Flash

    QSPI FLASH is connected to the GPIO port of the BANK500 in the PS section of the ZYNQ chip. In the system design, the GPIO port functions of these PS ports need to be configured as the QSPI FLASH interface. Figure 2-4-1 shows the QSPI Flash in the schematic. www.alinx.com 20 / 57...

  • Page 21: Part 2.5: Emmc Flash

    ZYNQ system, such as storing ARM applications, system files and other user data files The specific models and related parameters of eMMC FLASH are shown in Table 2-5-1. Position Model Capacity Factory MTFC8GAKAJCN-4M 8G Byte Micron Table 2-5-1: eMMC FLASH Specification www.alinx.com 21 / 57...
  • Page 22 Pin Name Pin Number MMC_DAT0 PS_MIO13_500 AH18 MMC_DAT1 PS_MIO14_500 AG18 MMC_DAT2 PS_MIO15_500 AE18 MMC_DAT3 PS_MIO16_500 AF18 MMC_DAT4 PS_MIO17_500 AC18 MMC_DAT5 PS_MIO18_500 AC19 MMC_DAT6 PS_MIO19_500 AE19 MMC_DAT7 PS_MIO20_500 AD19 MMC_CMD PS_MIO21_500 AC21 MMC_CCLK PS_MIO22_500 AB20 MMC_RSTN PS_MIO23_500 AB18 www.alinx.com 22 / 57...

  • Page 23: Part 2.6: Clock Configuration

    PS system. The crystal is connected to the PS_PADI_503 and PS_PADO_503 pins of BANK503 of the ZYNQ chip. The schematic diagram is shown in Figure 2-6-2: Figure 2-6-2: Passive Crystal Oscillator for RTC www.alinx.com 23 / 57...
  • Page 24 The core board provides a differential 200MHz PL system clock source for the reference clock of the DDR4 controller. The crystal oscillator output is connected to the global clock (MRCC) of PL BANK64. This global clock can be www.alinx.com 24 / 57...

  • Page 25: Part 2.7: Led

    FPGA configuration program, the configuration LED light will light up. The LED Schematic in the Core Board is shown in Figure 2-7-1: 3.3V 1.8V ZYNQ (电源指示灯） BANK Ultra Scale+ (DONE指示灯） Figure 2-7-1: LED Schematic in the Core Board www.alinx.com 25 / 57...

  • Page 26: Part 2.8: Power Supply

    The core board uses a PMIC chip TPS6508641 to generate all the power required by the XCZU3EG chip. For the TPS6508641 power supply design, please refer to the power supply chip manual. The design block diagram is as follows: www.alinx.com 26 / 57...

  • Page 27: Part 2.9: Acu3Eg Core Board Size Dimension

    The core board has a total of four high-speed expansion ports. It uses four 120-pin inter-board connectors (J29/J30/J31/J32) to connect to the carrier board. The connectors used is Panasonic AXK5A2137YG, and the corresponding connector model in the carrier board is Panasonic AXK6A2337YG. Among www.alinx.com 27 / 57...
  • Page 28 Signal Name J29 Pin Signal Name Pin Number Number B65_L2_N B65_L22_P B65_L2_P B65_L22_N B65_L4_N B65_L20_P B65_L4_P B65_L20_N B65_L1_N B65_L6_N B65_L1_P B65_L6_P B65_L7_P B65_L17_P B65_L7_N B65_L17_N B65_L15_P B65_L9_P B65_L15_N B65_L9_N B65_L16_P B65_L3_N B65_L16_N B65_L3_P B65_L14_P B65_L19_P B65_L14_N B65_L19_N www.alinx.com 28 / 57...
  • Page 29 B66_L3_P B65_L12_P B66_L3_N B65_L12_N B66_L1_P B65_L13_N B66_L1_N B65_L13_P B66_L6_P B65_L21_P B66_L6_N B65_L21_N B66_L16_P B65_L23_P B66_L16_N B65_L23_N B66_L15_P B66_L5_N B66_L15_N B66_L5_P B66_L4_P B66_L2_P B66_L4_N B66_L2_N B66_L11_P B66_L20_P B66_L11_N B66_L20_N B66_L12_P B66_L7_P B66_L12_N B66_L7_N B66_L13_N B66_L10_P B66_L13_P B66_L10_N www.alinx.com 29 / 57...
  • Page 30 B66_L14_N FPGA_TCK B66_L22_P FPGA_TDO B66_L22_N FPGA_TMS B66_L19_N B66_L21_N B66_L19_P B66_L21_P B66_L24_P B66_L17_P B66_L24_N B66_L17_N B66_L23_N B25_L9_P B66_L23_P B25_L9_N B25_L5_N B25_L10_P B25_L5_P B25_L10_N B66_L18_N B25_L12_P B66_L18_P B25_L12_N B25_L4_N B25_L11_P B25_L4_P B25_L11_N B26_L11_P B25_L6_N B26_L11_N B25_L6_P B26_L10_N B26_L6_N www.alinx.com 30 / 57...
  • Page 31 B26_L9_N B26_L2_N B26_L9_P B26_L2_P B26_L5_N B26_L4_N B26_L5_P B26_L4_P B26_L1_P B26_L12_P B26_L1_N B26_L12_N 505_CLK2_P 505_CLK1_P 505_CLK2_N 505_CLK1_N 505_CLK0_P 505_CLK3_P 505_CLK0_N 505_CLK3_N 505_TX3_P 505_TX1_P 505_TX3_N 505_TX1_N 505_RX3_P 505_TX0_P 505_RX3_N 505_TX0_N 505_TX2_P 505_RX1_P 505_TX2_N 505_RX1_N 505_RX2_P 505_RX0_P 505_RX2_N 505_RX0_N www.alinx.com 31 / 57...
  • Page 32 AG13 B24_L3_N AH13 B44_L12_N B44_L9_P AA11 B44_L12_P AB10 B44_L9_N AA10 B44_L10_N B44_L3_P AH12 B44_L10_P B44_L3_N AH11 B24_L11_N B44_L1_N AH10 B24_L11_P B44_L1_P AG10 B24_L9_N B24_L4_P AE13 B24_L9_P B24_L4_N AF13 B24_L8_P AB15 B44_L5_P AE12 B24_L8_N AB14 B44_L5_N AF12 www.alinx.com 32 / 57...
  • Page 33 224_RX2_N 224_TX2_N 224_RX1_P 224_TX1_P 224_RX1_N 224_TX1_N 224_RX0_P 224_TX0_P 224_RX0_N 224_TX0_N Pin assignment of board to board connector J32 J32 Pin Signal Name Pin Number J32 Pin Signal Name Pin Number PS_MIO35 PS_MIO30 PS_MIO29 PS_MIO31 PS_MIO58 PS_MIO53 www.alinx.com 33 / 57...
  • Page 34 PS_MIO54 PS_MIO37 PS_MIO27 PS_MIO28 PS_MIO77 PS_MIO59 PS_MIO76 PS_MIO60 PS_MIO61 PS_MIO39 PS_MIO62 PS_MIO38 PS_MIO63 PS_MIO65 PS_MIO40 PS_MIO66 PS_MIO44 PS_MIO67 PS_MIO45 PS_MIO68 PS_MIO47 PS_MIO64 PS_MIO48 PS_MIO69 PS_MIO41 PS_MIO74 PS_MIO32 PS_MIO73 PS_MIO46 PS_MIO72 PS_MIO50 PS_MIO71 PS_MIO49 PS_MIO75 PS_MIO34 PS_MIO70 www.alinx.com 34 / 57...
  • Page 35 ZYNQ Ultrascale + FPGA Board AXU3EG User Manual PS_MIO26 PS_MIO43 PS_MIO24 AB19 PS_MIO51 PS_MIO25 AB21 PS_MIO42 PS_MIO33 VCCO_65 VCCO_66 VCCO_65 VCCO_66 VCCO_65 VCCO_66 +12V +12V +12V +12V +12V +12V +12V +12V +12V +12V +12V +12V +12V +12V www.alinx.com 35 / 57...

  • Page 36: Part 3: Carrier Board

     2-Channel 10/100M/1000M Ethernet RJ-45 interface  2-Channel USB Uart Interfaces  1-Channel Micro SD card slot  1-Channel MIPI camera interface  2-Channel 40-pin expansion port  2-Channel CAN communication interfaces  2-Channel 485 communication interfaces www.alinx.com 36 / 57...

  • Page 37: Part 3.2: M.2 Interface

    Si5332 chip, the frequency is 100Mhz, and the schematic diagram of the M.2 circuit design is shown in Figure 3-2-1: PCIE_TX_P PCIE_TX_C_P PCIE_TX_N PCIE_TX_C_N ZYNQ BANK PCIE_RX_P Ultra PCIE_RX_N Scale+ 505_PCIE_REFCLK_P PCIE_REFCLK_P Si5332 PCIE_REFCLK_N 505_PCIE_REFCLK_N PCIE_RSTn_MIO37 M2_PCIE_RST_N 电平转换 Figure 3-2-1: M.2 Interface Schematic www.alinx.com 37 / 57...

  • Page 38: Part 3.3: Dp Interface

    MGT are connected to the DP connector in a differential signal mode. The DisplayPort auxiliary channel is connected to the MIO pin of the PS. The schematic diagram of the DP output interface design is shown in Figure 3-3-1: www.alinx.com 38 / 57...
  • Page 39 DP Reference Clock 505_CLK1_P 505_CLK2_P Positive DP Reference Clock 505_CLK1_N 505_CLK2_N Negative DP_AUX_OUT PS_MIO27 DP Auxiliary Data Output DP_AUX_IN PS_MIO30 DP Auxiliary Data Input DP_OE PS_MIO29 DP Auxiliary Data Output Enable DP_HPD PS_MIO28 DP Insertion Signal Detection www.alinx.com 39 / 57...

  • Page 40: Part 3.4: Usb3.0 Interface

    Signal Name Pin Name Pin Number Description USB_SSTXP 505_TX1_P USB3.0 Data Transmit Positive USB_SSTXN 505_TX1_N USB3.0 Data Transmit Negative USB_SSRXP 505_RX1_P USB3.0 Data Receive Positive USB_SSRXN 505_RX1_N USB3.0 Data Receive Negative USB_DATA0 PS_MIO56 USB2.0 Data Bit0 www.alinx.com 40 / 57...

  • Page 41: Part 3.5: Gigabit Ethernet Interface

    CLK125_EN Enable 125Mhz clock output selection Enable LED_MODE LED light mode configuration Single LED light mode 10/100/1000 adaptive, compatible Link adaptation and full duplex MODE0~MODE3 with full-duplex, half-duplex configuration Table 3-5-1: PHY chip default configuration value www.alinx.com 41 / 57...
  • Page 42 Ethernet 1 Transmit data bit0 PHY1_TXD1 PS_MIO66 Ethernet 1 Transmit data bit1 PHY1_TXD2 PS_MIO67 Ethernet 1 Transmit data bit2 PHY1_TXD3 PS_MIO68 Ethernet 1 Transmit data bit3 PHY1_TXCTL PS_MIO69 Ethernet 1 Transmit Enable Signal PHY1_RXCK PS_MIO70 Ethernet 1 RGMII Receive Clock www.alinx.com 42 / 57...

  • Page 43: Part 3.6: Usb To Serial Port

    PC's USB port for serial data communication. The schematic diagram of the USB Uart circuit design is shown in the figure below: The schematic diagram of the USB Uart circuit design is shown in Figure 3-6-1: www.alinx.com 43 / 57...

  • Page 44: Part 3.7: Sd Card Slot Interface

    ZU3EG. Since the VCCMIO of the BANK is set to 1.8V, but the data level of the SD card is 3.3V, connected through the TXS02612 level shifter. The schematic of the Zynq7000 PS and SD card connector is shown in Figure 3-10-1: www.alinx.com 44 / 57...

  • Page 45: Part 3.8: Expansion Header

    Part 3.8: Expansion Header The AXU3EG board is reserved with two 0.1-inch standard pitch 40-pin expansion ports J45 and J46, which are used to connect the ALINX modules or the external circuit designed by the user. The expansion port has 40 signals, of which 1-channel 5V power supply, 2-channel 3.3 V power supply, 3-channle...
  • Page 46 Signal Name Pin Number B43_L2_N AG11 B43_L2_P AF11 B44_L8_N AB14 B44_L8_P AB15 B44_L9_N B44_L9_P B44_L11_N B44_L11_P B43_L10_N B43_L10_P B43_L12_N B43_L12_P AB10 B44_L3_N AH13 B44_L3_P AG13 B44_L12_N AA12 B44_L12_P B44_L1_N AE14 B44_L1_P AE15 B44_L5_N AD14 B44_L5_P AD15 www.alinx.com 46 / 57...

  • Page 47: Part 3.9: Can Communication Interface

    The connection of the CAN transceiver chip on the PS side is show as Figure 3-9-1 PS_CAN1_RX CANH SN65HVD232 PS_CAN1_TX CANL ZYNQ BANK Ultra Scale+ PS_CAN2_RX CANH SN65HVD232 PS_CAN2_TX CANL Figure 3-9-1: Connection diagram of CAN transceiver chip on PS side www.alinx.com 47 / 57...

  • Page 48: Part 3.10: 485 Communication Interface

    Scale+ PL_485_RXD2 PL_485_TXD2 MAX3485 PL_485_DE2 Figure 3-3-1: 485 Communication on the PL Side The 485 communication pins are assigned as follows: Signal Name Pin Name Pin Number Description PL_485_TXD1 B43_L1_N AH10 The 1 Channel 485 Transceiver www.alinx.com 48 / 57...

  • Page 49: Part 3.11: Mipi Camera Interface

    Part 3.11: MIPI camera interface The AXU3EG carrier board includes a MIPI camera interface, which can be used to connect with the ALINX Brand MIPI OV5640 camera module AN5641. MIPI interface 15PIN FPC connector, 2 LANE data and 1 pair of clock, connected to the differential IO pin of BANK65, the level standard is 1.2V;...

  • Page 50: Part 3.12: Jtag Debug Port

    ZYNQ UltraScale+ chip by plugging and unplugging under power, we aded a protection diode to the JTAG signal to ensure that the signal voltage is within the range accepted by the FPGA and avoid damage to the ZYNQ UltraScale+ chip. www.alinx.com 50 / 57...

  • Page 51: Part 3.13: Real-Time Clock

    5V) to supply power to the clock chip. The BT1 on the development board is a battery Socket. After we put the coin battery, even the system is off, the coin battery can also power the RTC system and provide continuous time information. www.alinx.com 51 / 57...

  • Page 52: Part 3.14: Eeprom And Temperature Sensor

    ZYNQ UltraScale+ through the I2C bus. Figure 3-14-1 is the schematic diagram of EEPROM and temperature sensor LM75 ZYNQ BANK Ultra PS_IIC1_SCL 电平转 PS_IIC_B_SCL EEPROM PS_IIC1_SDA 换 PS_IIC_B_SDA Scale+ Figure 3-14-1: EEPROM and Sensor connection diagram www.alinx.com 52 / 57...

  • Page 53: Part 3.15: User Leds

    Figure 3-15-1: The User LEDs Hardware Connection Diagram Pin assignment of user LED lights Signal Name ZYNQ Pin Name ZYNQ Pin Number Description PS_LED1 PS_MIO40 User LED controlled by PS PL_LED1 B43_L5_P AE12 User LED controlled by PL www.alinx.com 53 / 57...

  • Page 54: Part 3.16: Keys

    There is a 4-digit DIP switch SW1 on the FPGA development board to configure the startup mode of the ZYNQ system. The AXU3EG system development platform supports 4 startup modes. The 4 startup modes are JTAG debug mode, QSPI FLASH, EMMC and SD2.0 card startup mode. After www.alinx.com 54 / 57...

  • Page 55: Part 3.18: Power Supply

    MP1482. In addition, the Carrier board generates +1.2V through LDO to supply power to the core board BANK65, and the power supply of BANK66 is +1.8V. The schematic diagram of the power supply design on the board is shown in Figure 3-18-1: www.alinx.com 55 / 57...

  • Page 56: Part 3.19: Alinx Customized Fan

    Ethernet, USB2.0, SD, DP, CAN, RS485 +1.2V BANK65 of Core Board Part 3.19: ALINX Customized Fan Because AXU3EG generates a lot of heat when it works normally, we add a heat sink and fan to the chip on the board to prevent the chip from overheating.

  • Page 57: Part 3.20: Carrier Board Size Dimension

    The fan has been screwed to the AXUEG FPGA development board before leaving the factory. The power of the fan is connected to the socket of J24. The red is positive and the black is negative. Part 3.20: Carrier Board Size Dimension Figure 3-20-1: Top View www.alinx.com 57 / 57...

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