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AWARD BIOS
Chipset Features à DRAM ECC Function
DRAM ECC
Function
Enabled
Disabled
Chipset Features à CPU-to-PCI IDE Posting
CPU-to-PCI IDE
Posting
Enabled
Disabled
Chipset Features à Video BIOS Cacheable
Video BIOS
Cacheable
Enabled
Disabled
Chipset Features à Video RAM Cacheable
Video RAM
Cacheable
Enabled
Disabled
Chipset Features à 8 Bit I/O Recovery Time
8 Bit I/O Recovery
Time
1
2
3
4
5
6
7
8
NA
3-14
This item lets you enable or disable DRAM ECC
function. The ECC algorithm has the ability to detect
double bit error and automatically correct single bit
error.
To enable or disable CPU to PCI IDE post write cycle.
The IDE write cycles will be queued in the FIFO or
buffer, and CPU can be released to do next job.
Disable it, if you find any IDE compatibility problem.
Allows the video BIOS to be cached to allow faster
video performance.
This item lets you cache Video RAM A000 and B000.
For some old I/O chips, after the execution of an I/O
command, the device requires a certain amount of
time (recovery time) before the execution of the next
I/O command. Because of new generation CPU and
mainboard chipset, the assertion of I/O command is
faster, and sometimes shorter than specified I/O
recovery time of old I/O devices. This item lets you
specify the delay of 8-bit I/O command by count of
ISA bus clock. If you find any unstable 8-bit I/O card,
you may try to extend the I/O recovery time via this
item. The BIOS default value is 4 ISA clock. If set to
NA, the chipset will insert 3.5 system clocks.
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