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IA
IB
From Phase
IC
Currents
To Channel
Transmitter
SPACE 1
MARK 1
SPACE 2
From Channel
Receiver
MARK 2
EXTERNAL
CHANNEL FAILURE 1
EXTERNAL
CHANNEL FAILURE 2
NOTE:
Hardware Function
XOR DEFINITION
INPUT 1
INPUT 2
OUTPUT
0
0
0
0
1
1
1
0
1
1
1
0
"0" – Logic 0
"1" – Logic 1
FD2
Fault
FD2
Detector 2
LN
Sequence
Network Filter
IKEY, LP
IT
COMPARERS
LN = – LP
C0, C1, C2
IKEY
TEST
IKEY
S1
M1
COMM
S2
M2
ECF
X0R
3
M1
S1
2
COMM
"0"
X0R
3
M2
S2
2
COMM
"0"
SYSTEM SETTINGS IN BOLD LETTERS
Figure L-2: REL 352 Logic Diagram
COMMUNICATION INTERFACE
AND COMPARISON
LN1
LDT1
S1
TERM
LN2
3
LDT2
S2
2
LP
"1"
LP1
LDT1
M1
TERM
LP2
3
LDT2
M2
2
"1"
IK0
2 CDT
"1"
SETTING
COMM
3
TERM
CHANNEL FAILURE / LOW RECEIVE
LEVEL DETECTION
(2)
75/0
3
2 TERM
(2)
"1"
75/0
(2) timers are 20% higher for 50Hz systems
CHOK
COMM
3
2
"0"
CHOK
COMM INTFCE 2 STATE (AM PLC) OR 3 STATE (FM PLC)
# OF TERMINALS 2 OR 3 TERMINAL LINE
"1"
2
3
ECF
TD296.OH sub 2
Sheet 1 of 3
CIN
COMM
CHOK
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