Low Intermediate Frequency (If) And Receiver Back-End; Uhf Band 1 (403-470 Mhz) 25-40 W Ldmos Transmitter Power Amplifier - Motorola CDM Series Detailed Service Manual

UHF Band 1 (403–470 MHz) 25–40 W LDMOS Transmitter Power Amplifier (PA) 40W
2.4

Low Intermediate Frequency (IF) and Receiver Back-End

The 44.85 high IF signal from the second IF amplifier feeds the IF IC (U3101) at pin1. Within the IF
IC the 44.85 MHz high IF signal mixes with the 44.395 MHz second local oscillator (2nd LO) to
produce the low IF signal at 455 kHz. The 2nd LO frequency is determined by crystal Y3101. The
low IF signal is amplified and filtered by an external pair of 455 kHz ceramic filters FL3112, FL3114
for 20/25 kHz channel spacing or FL3111,FL3113/F3115 for 12.5 kHz channel spacing. These pairs
are selectable via BWSELECT. The filtered output from the ceramic filters is applied to the limiter
input pin of the IF IC (pin 14).
The IF IC contains a quadrature detector using a ceramic phase-shift element (Y3102) to provide
audio detection. Internal amplification provides an audio output level of 120 mV rms (at 60%
deviation) from U3103 pin 8 (DISCAUDIO) which is fed to the ASFIC_CMP (U0221) pin 2 (part of
the controller circuitry).
A Receive Signal Strength Indicator (RSSI) signal is available at U3101 pin 5, having a dynamic
range of 70 dB. The RSSI signal is interpreted by the µP (U0101 pin 63) and in addition is available
at accessory connector J0501-15.
3.0 UHF Band 1 (403–470 MHz) 25–40 W LDMOS Transmitter Power
Amplifier (PA) 40W
The radio's 40W PA is a three-stage amplifier used to amplify the output from the VCOBIC to the
radio transmit level. All three stages utilize LDMOS technology. The gain of the first stage (U4401) is
adjustable, controlled by pin 4 of PCIC (U4501). It is followed by an LDMOS stage (Q4421) and
LDMOS final stage (Q4441).
From VCO
Controlled
Stage
Vcontrol
To Microprocessor
Devices U4401, Q4421 and Q4441 are surface mounted. A pressure pad between the board and
the radio's cover provides good thermal contact between the devices and the chassis.
PA
PA-Final
Driver
Stage
Bias 2 & Bias 3
A S F I C _ C M P
SPI BUS
Bias 1
Figure 12-2 UHF Transmitter Block Diagram
Pin Diode
Antenna
Switch
Power
Sense
PA
PWR
SET
Temperature
P C I C
Section 12: 2-3
Antenna
Harmonic
Filter
RF Jack
Sense
To Microprocessor
6881091C63-F