First Power Controlled Stage; Power Controlled Driver Stage; Final Stage - Motorola CDM Series Detailed Service Manual

Section 6: 2-4
3.1

First Power Controlled Stage

The first stage (U5401) is a 20 dB gain integrated circuit containing two LDMOS FET amplifier
stages. It amplifies the RF signal from the VCO (TXINJ). The output power of stage U5401 is
controlled by a DC voltage applied to pin 1 from the op-amp U5402-1, pin 1. The control voltage
simultaneously varies the bias of two FET stages within U5401. This biasing point determines the
overall gain of U5401 and therefore its output drive level to Q5421, which in turn controls the output
power of the PA.
Op-amp U5402-1 monitors the drain current of U5401 via resistor R5444 and adjusts the bias
voltage of U5401 so that the current remains constant. The PCIC (U5501) provides a DC output
voltage at pin 4 (INT) which sets the reference voltage of the current control loop. A rising power
output causes the DC voltage from the PCIC to fall, and U5402-1 adjusts the bias voltage for a lower
drain current to lower the gain of the stage.
In receive mode the DC voltage from PCIC pin 23 (RX) turns on Q5442, which in turn switches off
the biasing voltage to U5401.
Switch S5440 is a pressure pad with a conductive strip which connects two conductive areas on the
board when the radio's cover is properly screwed to the chassis. When the cover is removed, S5440
opens and the resulting high voltage level at the inverting inputs of the current control op-amps
U5402-1 & 2 switches off the biasing of U5401 and Q5421. This prevents transmitter key up while
the devices do not have proper thermal contact to the chassis.
3.2

Power Controlled Driver Stage

The next stage is an LDMOS device (Q5421) providing a gain of 12dB. This device requires a
positive gate bias and a quiescent current flow for proper operation. The bias is set during transmit
mode by the drain current control op-amp U5402-2, and fed to the gate of Q5421 via the resistive
network R5429, R5418, R5415 and R5416.
Op-amp U5402-2 monitors the drain current of U5421 via resistors R5424-27 and adjusts the bias
voltage of Q5421 so that the current remains constant. The PCIC (U5501) provides a DC output
voltage at pin 4 (INT) which sets the reference voltage of the current control loop. A rising power
output causes the DC voltage from the PCIC to fall, and U5402-2 adjusts the bias voltage for a lower
drain current to lower the gain of the stage.
In receive mode the DC voltage from PCIC pin 23 (RX) turns on Q5422, which in turn switches off
the biasing voltage to Q5421.
3.3

Final Stage

The final stage is an LDMOS device (Q5441) providing a gain of 12dB. This device also requires a
positive gate bias and a quiescent current flow for proper operation. The voltage of the line
MOSBIAS_2 is set in transmit mode by the ASFIC and fed to the gate of Q5441 via the resistive
network R5404, R5406, and R5431-2. This bias voltage is tuned in the factory. If the transistor is
replaced, the bias voltage must be tuned using the Global Tuner. Care must be taken not to damage
the device by exceeding the maximum allowed bias voltage. The device's drain current is drawn
directly from the radio's DC supply voltage input, PASUPVLTG, via L5436 and L5437.
A matching network consisting of C5441-49 and striplines transforms the impedance to 50 ohms
and feeds the directional coupler.
6881091C63-F
UHF Band 2 (450–512/527 MHz) 1–25 W Transmitter Power Amplifier (PA) 25 W