Motorola CDM Series Detailed Service Manual page 346

Section 7: 2-10
To reduce synthesizer lock time when new frequency data has been loaded into the synthesizer the
magnitude of the loop current is increased by enabling the IADAPT (U1201-45) for a certain
software programmable time (Adapt Mode). The adapt mode timer is started by a low to high
transition of the CSX line. When the synthesizer is within the lock range, the current is determined
only by the resistors connected to BIAS 1, BIAS 2, or the internal current source. A settled
synthesizer loop is indicated by a high level of signal LOCK (U1201-4).
In order to modulate the PLL the two-spot modulation method is utilized. Via pin 10 (MODIN) on
U1201, the audio signal is applied to both the A/D converter (low frequency path) and the balanced
attenuator (high frequency path). The A/D converter converts the low frequency analog modulating
signal into a digital code that is applied to the loop divider, thereby causing the carrier to deviate.
The balance attenuator is used to adjust the VCO's deviation sensitivity to high frequency
modulating signals. The output of the balance attenuator is present at the MODOUT port
(U1201-41) and superimposed on the VCO steering line voltage by a divider consisting of C1215,
C1208 and C1212.
NOTE For Low Band models only, both 20 kHz and 25 kHz channel spacings give the same
maximum system deviation of 5 kHz; they can be used interchangeably in this manual as
well as in the CPS.
6881091C63-F
Low Band Frequency Synthesis