Holtek HT48RA5 Technical Document page 12

The port A wake-up and interrupt methods can be con-
sidered as a continuation of normal execution. Each bit
in port A can be independently selected to wake up the
device by mask option. Awakening from an I/O port stim-
ulus, the program will resume execution of the next in-
struction. If it awakens from an interrupt, two sequence
may occur. If the related interrupt is disabled or the inter-
rupt is enabled but the stack is full, the program will re-
sume execution at the next instruction. If the interrupt is
enabled and the stack is not full, the regular interrupt re-
sponse takes place. If an interrupt request flag is set to
²1² before entering the HALT mode, the wake-up func-
tion of the related interrupt will be disabled. Once a
wake-up event occurs, it takes 1024 t
period) to resume normal operation. In other words, a
dummy period will be inserted after a wake-up. If the
wake-up results from an interrupt acknowledge signal,
the actual interrupt subroutine execution will be delayed
by one or more cycles. If the wake-up results in the next
instruction execution, this will be executed immediately
after the dummy period is finished.
To minimize power consumption, all the I/O pins should
be carefully managed before entering the HALT status.
Reset
There are three ways in which a reset can occur:
·
RES reset during normal operation
·
RES reset during HALT
·
WDT time-out reset during normal operation
The WDT time-out during HALT is different from other
chip reset conditions, since it can perform a ²warm re -
set² that resets only the program counter and SP, leav-
ing the other circuits in their original state. Some regis-
ters remain unchanged during other reset conditions.
Most registers are reset to the ²initial condition² when
the reset conditions are met. By examining the PDF and
TO flags, the program can distinguish between different
²chip resets².
TO PDF RESET Conditions
0 0 RES reset during power-up
u u RES reset during normal operation
0 1 RES wake-up HALT
1 u WDT time-out during normal operation
1 1 WDT wake-up HALT
Note: ²u² stands for unchanged
To guarantee that the system oscillator is started and
stabilized, the SST (System Start-up Timer) provides an
extra-delay of 1024 system clock pulses when the sys-
tem reset (power-up, WDT time-out or RES reset) or the
system awakes from the HALT state.
When a system reset occurs, the SST delay is added
during the reset period. Any wake-up from HALT will en-
able the SST delay.
Rev. 1.40
The functional unit chip reset status are shown below.
Program Counter
Interrupt
Prescaler
WDT
Timer/event Counter
Input/output Ports
Stack Pointer
(system clock
SYS
S S T T i m e - o u t
C h i p
1 0 0 k W
0 . 1 m F
Note:
O S C 1
12
HT48RA5/HT48CA5
000H
Disable
Clear
Clear. After master reset,
WDT begins counting
Off
Input mode
Points to the top of the stack
V D D
R E S
R e s e t
Reset Timing Chart
V
V
D D
D D
1 0 0 k W
R E S
1 0 k W
B a s i c
R e s e t
0 . 1 m F
C i r c u i t
Reset Circuit
Most applications can use the Basic Reset Cir-
cuit as shown, however for applications with ex-
tensive noise, it is recommended to use the
Hi-noise Reset Circuit.
H A L T
W D T
R E S
S S T
1 0 - b i t R i p p l e
C o u n t e r
S y s t e m R e s e t
Reset Configuration
t
S S T
0 . 0 1 m F
R E S
H i - n o i s e
R e s e t
C i r c u i t
W a r m R e s e t
C o l d
R e s e t
May 22, 2009